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UART standalone driver

UART standalone driver

This page gives an overview of PS UART BareMetal driver which is available as part of the Xilinx Vivado and SDK distribution.

Table of Contents



Introduction

The UART controller is a full-duplex asynchronous receiver and transmitter that supports a
wide range of programmable baud rates and I/O signal formats. The controller can
accommodate automatic parity generation and multi-master detection mode.

The UART operations are controlled by the configuration and mode registers. The state of
the FIFOs, modem signals, and other controller functions are read using the status, interrupt
status, and modem status registers.

For more details, please refer zynqmp TRM which includes link s to the official documentation and resource utilization. 


Driver Sources

The source code for the driver is included with the Vitis Unified Software Platform installation, as well as being available in the Xilinx Github repository. 

Driver Name

Path in Vitis

Path in Github

Driver Name

Path in Vitis

Path in Github

uartps

<Vitis Install Directory>/data/embedded/XilinxProcessorIPLib/drivers/uartps

https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/uartps



Note: To view the sources for a particular release, use the rel-version tag in github.  For example, for the 2020.1 release, the proper version of the code is https://github.com/Xilinx/embeddedsw/tree/xilinx-v2020.1/XilinxProcessorIPLib/drivers/uartps



The driver source code is organized into different folders.  The table below shows the uartps driver source organization. 



Directory

Description

Directory

Description

doc

Provides the API and data structure details

data

Driver .tcl, .yaml and .mdd file

examples

Example applications that show how to use the driver features

src

Driver source files, make and cmakelists file

Note: AMD Xilinx embeddedsw build flow has been changed from 2023.2 release to adapt to the new system device tree based flow. For further information, refer to the wiki link Porting embeddedsw components to system device tree (SDT) based flow
The .yaml(in data folder) and CMakeLists.txt(in src folder) files are needed for the System Device Tree based flow. The Driver .tcl and .mdd files are for the older build flow which will be deprecated in future.

Driver Implementation

For a full list of features supported by this IP, please refer zynqmp TRM which includes link s to the official documentation and resource utilization. 

Features

Programmable baud rate generator
64-byte receive and transmit FIFOs
Programmable protocol:
6, 7, or 8 data bits
1, 1.5, or 2 stop bits
Odd, even, space, mark, or no parity
Parity, framing and overrun error detection
Line-break generation and detection
Interrupts generation
RxD and TxD modes: Normal/echo and diagnostic loopbacks using the mode switch

The following features are supported in the uartps Standalone driver.
Loop UART 0 with UART 1 option
Modem control signals: CTS, RTS, DSR, DTR, RI and DCD are available only on the EMIO interface

Known Issues and Limitations

None

Example Applications

Refer to the driver examples directory for various example applications that exercise the different features of the driver. Each application is linked in the table below. The following sections describe the usage and expected output of the various applications.  These example applications can be imported into the Vitis IDE from the Board Support Package  settings tab. 

Links to Examples

Examples Path:

https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/uartps/examples





Test name

Example Source

Description

Test name

Example Source

Description

Uart Interrupt example

xuartps_intr_example.c

This example does basic read and write test with interrupts.

Uart polled example

xuartps_polled_example.c

This example does basic read and write test using polling.

Uart hello world example

xuartps_hello_world_example.c

This example prints a string.

Uart selftest_example

xuartps_selftest_example.c

This example performs the basic selftest using the driver.

Uart low_echo_example

xuartps_low_echo_example.c

This example shows the usage of the low-level driver functions and macros of the driver.

Example Application Usage

Uart Interrupt example

This example does basic read and write test with interrupts.

Expected Output



Successfully ran UART Interrupt Example Test

Uart polled example



This example does basic read and write test using polling.

Expected Output



Successfully ran UART Polled Mode Example Test

Uart hello world example



This example prints a string.

Expected Output



HelloWorld Successfully ran Uartps hello world Example

Example Design Architecture

NA



Change Log

2025.1

https://github.com/Xilinx/embeddedsw/blob/xlnx_rel_v2025.1/doc/ChangeLog#L189

2024.2

https://github.com/Xilinx/embeddedsw/blob/xlnx_rel_v2024.2/doc/ChangeLog#L262

2024.1

https://github.com/Xilinx/embeddedsw/blob/xlnx_rel_v2024.1/doc/ChangeLog#L942

2023.2

https://github.com/Xilinx/embeddedsw/blob/xlnx_rel_v2023.2/doc/ChangeLog#L141

2023.1

https://github.com/Xilinx/embeddedsw/blob/xilinx_v2023.1/doc/ChangeLog#L141

2022.2

None



2021.2

None

2021.1



https://github.com/Xilinx/embeddedsw/blob/xilinx_v2021.1/doc/ChangeLog#L487

2020.2



https://github.com/Xilinx/embeddedsw/blob/xilinx-v2020.2/doc/ChangeLog#L395

2020.1



https://github.com/Xilinx/embeddedsw/blob/xilinx-v2020.1/doc/ChangeLog#L133

2019.2



None

2019.1



None

2018.3



https://github.com/Xilinx/embeddedsw/blob/xilinx-v2018.3/doc/ChangeLog#L312

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