Introduction

The XilFlash library provides read/write/erase/lock/unlock features to access a parallel flash device.
This library implements the functionality for flash memory devices that conform to the "Common Flash Interface" (CFI) standard. CFI allows a single flash library to be used for an entire family of parts and helps us determine the algorithm to utilize during runtime. All the calls in the library are blocking in nature in that the control is returned back to user only after the current operation is completed successfully or an error is reported.

Device Geometry

The device geometry varies for different flash device families. Following sections describes the geometry of
different flash device families:

Intel Flash Device Geometry

Flash memory space is segmented into areas called blocks. The size of each block is based on a power of 2. A
region is defined as a contiguous set of blocks of the same size. Some parts have several regions while others have one. The arrangement of blocks and regions is referred to by this module as the part's geometry. Some Intel flash supports multiple banks on the same device. This library supports single and multiple bank flash devices.

AMD Flash Device Geometry

Flash memory space is segmented into areas called banks and further in to regions and blocks. The size of
each block is based on a power of 2. A region is defined as a contiguous set of blocks of the same size. Some
parts have several regions while others have one. A bank is defined as a contiguous set of blocks. The bank may contain blocks of different size. The arrangement of blocks, regions and banks is referred to by this module as the part's geometry.
The cells within the part can be programmed from a logic 1 to a logic 0 and not the other way around. Tochange a cell back to a logic 1, the entire block containing that cell must be erased. When a block is erased all bytes contain the value 0xFF. The number of times a block can be erased is finite. Eventually the block will wear out and will no longer be capable of erasure. As of this writing, the typical flash block can be erased 100,000 or more times.

How to Enable

xilflash library can be found at

https://github.com/Xilinx/embeddedsw/tree/master/lib/sw_services/xilflash

xilflash

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-data - Provides the API and data structure details

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-src - Driver source files which are further organised into

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-examples - Contains example applications demonstrating the use of xilflash libray

Select the xilflash library in Vitis

• Select Flash family as below

enable_intel-> Enables support for Intel family devices

enable_amd-> Enables support for AMD family device

Features support

This xilflash library supports basic operations like read(),write(),erase() etc as below

• DeviceControl

• Read

• Write

• Erase

• SectorProtection

Example Application

• Device control example

• Sector protection example

• Flash based read/write

Following is the list of supported parallal flash parts

Known issues and limitations

Test cases

Test case ran by taking examples from example folder specified above

Changelog

2023.2

https://github.com/Xilinx/embeddedsw/blob/xilinx_v2023.2/doc/ChangeLog#L532

2023.1

None

2022.2

None

2022.1

None

2021.2

None

2021.1

https://github.com/Xilinx/embeddedsw/blob/xilinx_v2021.1/doc/ChangeLog#L329

2020.2

https://github.com/Xilinx/embeddedsw/blob/xilinx-v2020.2/doc/ChangeLog#L1192

2020.1

https://github.com/Xilinx/embeddedsw/blob/xilinx-v2020.1/doc/ChangeLog#L166

2019.2

https://github.com/Xilinx/embeddedsw/blob/xilinx-v2019.2/doc/ChangeLog#L431

2019.1

https://github.com/Xilinx/embeddedsw/blob/xilinx-v2019.1/doc/ChangeLog#L190

Related Links

• http://www.wiki.xilinx.com/Baremetal+Drivers+and+Libraries