BRAM Standalone driver

Owned by Confluence Wiki Admin (Unlicensed)
Last updated: Jun 03, 2024 by Shubhrajyoti Datta
2 min read

This page gives an overview of bram (block ram controller) driver which is available as part of the Xilinx Vivado and SDK distribution.

Table of Contents

Introduction

This page gives an overview of BRAM(block ram controller) driver which is available as part of the Xilinx Vivado and SDK distribution.

For more information, please refer BRAM which includes links to the official documentation and resource utilization. 

Driver Sources

The source code for the driver is included with the Vitis Unified Software Platform installation, as well as being available in the Xilinx Github repository. 

Driver Name

Path in Vitis

Path in Github

bram

<Vitis Install Directory>/data/embedded/XilinxProcessorIPLib/drivers/bram

https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/bram

Note: To view the sources for a particular release, use the rel-version tag in github.  For example, for the 2020.1 release, the proper version of the code is: https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/bram


The driver source code is organized into different folders.  The table below shows the ospipsv driver source organization. 

DirectoryDescription

doc

Provides the API and data structure details

data

Driver .tcl , .mdd and .yaml files

examples

Example applications that show how to use the driver features

src

Driver source files, make and cmakelists file

Note: AMD Xilinx embeddedsw build flow has been changed from 2023.2 release to adapt to the new system device tree based flow. For further information, refer to the wiki link Porting embeddedsw components to system device tree (SDT) based flow

The .yaml(in data folder) and CMakeLists.txt(in src folder) files are needed for the System Device Tree based flow. The Driver .tcl and .mdd files are for the older build flow which will be deprecated in future.

Driver Implementation

For a full list of features supported by this IP, please refer Chapter 73: Octal SPI Controller in TRM

Features

The Xilinx BRAM controller is a soft IP core designed for Xilinx FPGAs and contains the following general features,

  1. LMB v2.0 bus interfaces with byte enable support
  2. Separate read and write channel interfaces to utilize dual port FPGA BRAM technology
  3. Supports memory sizes up to a maximum of 2 MBytes
  4. Compatible with Xilinx AXI Interconnect
  5. Used in conjunction with bram_block peripheral to provide fast BRAM memory solution for MicroBlaze ILMB and DLMB ports
  6. Supports byte, half-word, and word transfers
  7. Supports optional BRAM error correction and detection

Known Issues and Limitations

  • None

Example Applications

Refer to the driver examples directory for various example applications that exercise the different features of the driver. Each application is linked in the table below. The following sections describe the usage and expected output of the various applications.  These example applications can be imported into the Vitis IDE from the Board Support Package  settings tab. 

Links to Examples

Examples Path:
https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/bram/examples


Test Name

Example Source

Description
BRAM example

xbram_example.c


This example initializes ECC for BRAM and executes the selftest.
OSPI Interrupt mode example

xbram_intr_example.c


This example configures interrupt for BRAM controller and evaluates triggering of interrupt through fault injection

Example Application Usage

BRAM selftest example

This example initializes ECC for BRAM and executes the selftest.

Expected Output


Successfully ran Bram Example

BRAM interrupt example


This example configures interrupt for BRAM controller and evaluates triggering of interrupt through fault injection
Output
Successfully ran Bram Interrupt Example

Changelog

2024.1

2023.2

2023.1

  • None

2022.2

2022.2

2022.1

  • None

2021.1

  • None

2020.2

  • None

2020.1

  • None

Related Links

© Copyright 2019 - 2022 Xilinx Inc. Privacy Policy