BRAM Standalone driver

BRAM Standalone driver


This page gives an overview of bram (block ram comtroller) driver which is available as part of the Xilinx Vivado and SDK distribution.
Source path for the driver:

Driver source code is organized into different folders. Below diagram shows the bram driver source organization

-- Doc - Provides the API and data structure details
- Examples - Reference application to show how to use the driver APIs and calling sequence
- Source - Driver source files

Features Supported

Controller/Driver features supported

The Xilinx BRAM controller is a soft IP core designed for Xilinx FPGAs and contains the following general features,
  • LMB v2.0 bus interfaces with byte enable support
  • Separate read and write channel interfaces to utilize dual port FPGA BRAM technology
  • Supports memory sizes up to a maximum of 2 MBytes
  • Compatible with Xilinx AXI Interconnect
  • Used in conjunction with bram_block peripheral to provide fast BRAM memory solution for MicroBlaze ILMB and DLMB ports
  • Supports byte, half-word, and word transfers
  • Supports optional BRAM error correction and detection

Known issues and Limitations


Test cases

BRAM selftest example
This example initializes ECC for BRAM and executes the selftest.

BRAM interrupt example
This example configures interrupt for BRAM controller and evaluates triggering of interrupt through fault injection



  • bram: Modify Makefile to support parallel make execution
  • Makefile: Remove realpath command


  • Fixed the warnings reported by ARMCC compiler


  • No changes


  • No Changes


  • Updated bram.tcl to add U suffix for all the macros exported into xparameters.h
  • Fixed compilation warnings in the driver

Related Links