BRAM Standalone driver
This page gives an overview of bram (block ram comtroller) driver which is available as part of the Xilinx Vivado and SDK distribution.
For more information, please refer BRAM which includes links to the official documentation and resource utilization.
The source code for the driver is included with the Vitis Unified Software Platform installation, as well as being available in the Xilinx Github repository.
The driver source code is organized into different folders. The table below shows the ospipsv driver source organization.
Provides the API and data structure details
Driver .tcl and .mdd file
Example applications that show how to use the driver features
Driver source files
For a full list of features supported by this IP, please refer Chapter 73: Octal SPI Controller in TRM
The Xilinx BRAM controller is a soft IP core designed for Xilinx FPGAs and contains the following general features,
- LMB v2.0 bus interfaces with byte enable support
- Separate read and write channel interfaces to utilize dual port FPGA BRAM technology
- Supports memory sizes up to a maximum of 2 MBytes
- Compatible with Xilinx AXI Interconnect
- Used in conjunction with bram_block peripheral to provide fast BRAM memory solution for MicroBlaze ILMB and DLMB ports
- Supports byte, half-word, and word transfers
- Supports optional BRAM error correction and detection
Known Issues and Limitations
Refer to the driver examples directory for various example applications that exercise the different features of the driver. Each application is linked in the table below. The following sections describe the usage and expected output of the various applications. These example applications can be imported into the Vitis IDE from the Board Support Package settings tab.
Links to Examples
|This example initializes ECC for BRAM and executes the selftest.|
|OSPI Interrupt mode example|
|This example configures interrupt for BRAM controller and evaluates triggering of interrupt through fault injection|
Example Application Usage
BRAM selftest example
This example initializes ECC for BRAM and executes the selftest.
Successfully ran Bram Example
BRAM interrupt example This example configures interrupt for BRAM controller and evaluates triggering of interrupt through fault injection Output
Successfully ran Bram Interrupt Example