Introduction

Information on the standalone emacps driver is provided on this page. GEM support on Versal, Zynq Ultrascale+ MPSoC, and Zynq is enabled with this driver.
Please consult the GEM Ethernet chapter in Versal TRM (AM011), Zynq TRM (UG585), or ZynqMP TRM (UG1085) for additional details.

Driver Sources

The driver's source code can be found in the Xilinx Github repository and is part of the Vitis Unified Software Platform installation.

Driver Name	Emacps
Vitis	<Vitis Install Directory>/data/embedded/XilinxProcessorIPLib/drivers/emacps
Github	https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/emacps

Note: To view the sources for a particular release, use the rel-version tag in github.
For example, for the 2021.1 release, the proper version of the code is
https://github.com/Xilinx/embeddedsw/tree/xilinx_v2021.1/XilinxProcessorIPLib/drivers/emacps

Driver source code organisation

├── data : Driver .tcl, .mdd file and .yaml files
├── examples : Example applications that show how to use the driver features
└── src : Driver source files, make and cmake files

AMD Xilinx embeddedsw build flow is changed from the 2023.2 release to adapt to new system device tree based flow.
For further information, refer to the wiki page
Porting embeddedsw components to system device tree (SDT) based flow - Xilinx Wiki - Confluence (atlassian.net).

The .yaml (in data/) and CMakeLists.txt (in src/) files are needed for the System Device Tree based flow.
The Driver .tcl and .mdd files are for the older build flow, which will be deprecated in the future.

Driver Implementation

For a full list of features supported by this IP, please refer to GEM Chapter in Zynq TRM (UG585), ZynqMP TRM (UG1085) or Versal TRM (AM011) for respective devices.

Features

Controller/Driver features supported

10/100/1000 speeds, phy/external loop back (supported in emacps

```
PHY management
```

DMA, Packet buffer support, Checksum offload, FCS stripping, programmable IPG, multicasting, promiscuous and broadcast modes.

Flow control and half duplex features are supported by controller but not demonstrated in the examples.

ZynqMP and Versal only: 64 bit descriptor support, Priority queue support, Jumbo frame support, CCI support

PHY configurations

emacps driver supports the following PHY configurations:

Family	PHY	Support
Zynq	RGMII	Yes - supported in HW and driver
ZynqMP	RGMII	Yes - supported in HW and driver
ZynqMP	SGMII	Yes - supported in HW and driver
Versal	RGMII	Yes - supported in HW and driver

Known Issues and Limitations

issues

1. The following features are not supported:

External FIFO interface - this driver only targets DMA

```
Partial store and forward not supported
```

2. Clock change is not automatically handled in the example in SDT flow currently. Clock registers can still be manually modified by users. Support for automatically handling this through baremetal clocking framework will be added in an upcoming release.

Corresponding legacy XPAR for clock divisors for 10/100/1000Mbps are also NOT exported in SDT flow (i.e. starting Vitis unified 2024.1 release)

3. XPAR properties for the following are not generated in SDT flow (i.e. starting Vitis unified 2024.1 release):

XPAR for GMII2RGMII in the design - This information is now automatically generated in SDT as "gmiitorgmii-addr". Use the corresponding GMII2RGMII PHY address entry in Config structure (starting 2025.1 release)
XPAR for Soft PCS/PMA in the design - This information is now automatically generated in SDT as "phy-mode". Use standard PHY scanning and identifier registers to detect PCS PMA (SGMII/1000BaseX) PHY in the design and PhyType in Config structure. Please see xemacpsif_physpeed.c in AMD lwip adapter implementation for reference.

Interop

PHY device Marvell 88E1116 has been tested on Zynq evaluation board

PHY devices Marvell 88E1512, TI DP83867 (RGMII and SGMII), VSC8211 and RTL8211 have been tested on ZynqMP.

PHY devices Marvell 88E1512, TI DP83867, VSC8531_02 and RTL8211DN have been tested on Versal.

Example Applications

Emacps driver supports a DMA based loopback example and it describes how its different features can be exercised. These example applications can be imported into the Vitis IDE from the Board Support Package settings tab.

Links to Examples

Examples Path:
https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/emacps

Test Name

Example Source

Description

Emacps DMA loopback example

xemacps_example_intr_dma.c

xemacps_example.h

xemacps_example_util.c

Emacps basic DMA loopback examples sends and receives a multiple single frames in loopback mode.
Refer to https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/emacps/examples/readme.txt for more information.

emacps 1588 examples were deprecated as they were originally added as a reference for Zynq-7000 but the timestamping logic in that version of the IP has issues, rendering this feature unusable. These examples were removed in 2021.1 release.

Example Application Usage

Emacps DMA loopback example

Emacps basic DMA loopback examples sends and receives multiple single frames in loopback mode.

Expected Output

Entering into main()
Packet: 1 Queue: 1 Payload size: 1751
Packet: 2 Queue: 0 Payload size: 2123
Packet: 3 Queue: 1 Payload size: 1482
Packet: 4 Queue: 0 Payload size: 6575
Packet: 5 Queue: 1 Payload size: 7552
Packet: 6 Queue: 0 Payload size: 2979
Packet: 7 Queue: 1 Payload size: 7200
Packet: 8 Queue: 0 Payload size: 8104
Packet: 9 Queue: 1 Payload size: 5449
Packet: 10 Queue: 0 Payload size: 1245
Packet: 11 Queue: 1 Payload size: 2054
Packet: 12 Queue: 0 Payload size: 3119
Total Packets sent: 12
Total Packets received: 12
Successfully ran Emacps intr dma Example

Example Design Architecture

NA

Performance

Standalone ethernet performance is benchmarked with the use of light weight IP library and application. Please refer to
http://www.wiki.xilinx.com/Standalone+LWIP+library#Performance