This page gives an overview of the bare-metal driver support for the Xilinx® LogiCORE™ IP Zynq USB soft IP. 

Table of Contents

Introduction

This page gives an overview of the Zynq usbps driver which available as part of the Xilinx Vivado and SDK distribution
For more information,

Please refer to Chapter 15: USB3.0 Controller in Zynq7000 TRM

Driver Sources

The source code for the driver is included with the Vitis Unified Software Platform installation and being available in the Xilinx Github repository. 

Note: To view the sources for a particular release, use the rel-version tag in github.  For example, for the 2020.1 release, the proper version of the code is: https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/usbps

The driver source code is organized into different folders.  The table below shows the usbps driver source organization. 

Driver Implementation

For a full list of features supported by this IP,

Please refer to Chapter 15: USB3.0 Controller in Zynq7000 TRM

Features Supported

Controller Features Supported

• USB 2.0 High-Speed Host controller (480 Mb/s).

• USB 2.0 HS and FS Device controller.

• USB 1.1 legacy FS/LS.

• On-the-Go, OTG 1.3 supplement.

• Local DMA Engine.

Features Driver support

• Support device mode only

Known Issues and Limitations:

• Host mode is not supported by the standalone driver

• OTG mode is not supported by the standalone driver

Example Applications

Refer to the driver examples directory for various example applications that exercise the different features of the driver. Each application is linked in the table below. The following sections describe the usage and expected output of the various applications.

These example applications can be imported into the Vitis IDE from the Board Support Package settings tab. 

Links to Examples

Examples Path:
https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/usbps/examples

Example Application Usage

USB 2.0 Peripheral Mode

The below gives the testing procedure of zynq USB standalone example which operates as a mass storage and audio gadget

Mass-Storage: USB Interrupt mode example

Mass storage profile can be tested by compiling  xusbps_class_storage.c,xusbps_class_storage.h,xusbps_ch9_storage.c,xusbps_ch9_storage.h,xusbps_ch9.c,xusbps_ch9.h and xusbps_intr_example.c
files together

Testing procedure

• Download and run the generated USB 2.0 example ELF

• Connect board setup to standard host(Windows/Linux)machine USB 2.0 port.

Expected Output

• You will get a pop-up window on the Window machine for formatting the size 256MB
  After the format complete you can copy a file to the USB device
  
  

  Open

  

Audio gadget

Audio profile can be tested by compiling xusbps_audio_example.c,xusbps_ch9_audio.c,xusbps_ch9_audio.h,xusbps_ch9.c,xusbps_ch9.h,

xusbps_class_audio.c,xusbps_class_audio.h and xusbps_audiodata.h files.

Audio example supports either UAC1.0 or UAC2.0.By default audio example runs on UAC1.0.

Testing procedure

• Download and run the generated USB 2.0 example ELF

• Connect board setup to standard host(Windows/Linux)machine USB 2.0 port.

• To enable UAC2.0 support, undefine MACRO  XUSBPS_UAC1 in xusbps_ch9_audio.h.   

Expected Output

Device Log:

Open

1. Audio UAC1.0 output at Host end

• Detection of HighSpeed Microphone – UAC1.0 on standard host Linux machine USB 2.0 port. 

Open

Open

Open

Open

Open

2. Audio UAC2.0 Output:

• UAC2.0 - Audio device detection and record/play an audio file from Host

• Check device entry with help of “aplay -l” or “arecord –l”   

Open

• First, play a file with help of “aplay” command

• host # aplay -v -D hw:1,0 -f S16_LE -r 48000 -c 2 <uac2_0_play.wav>

• Record a file with help of “arecord” command

• host # arecord -v -D hw:1,0 -f S16_LE -c 2 -r 44100 -d 10 <uac2_0_record.wav>

Example Design Architecture

Default Petalinux Design

Performance

The below performance results are observed using CrystalDiskMark tool on windows

USB 2.0:

Open

Change Log

2024.2

embeddedsw/doc/ChangeLog at xlnx_rel_v2024.2 · Xilinx/embeddedsw · GitHub

2024.1

embeddedsw/doc/ChangeLog at xlnx_rel_v2024.1 · Xilinx/embeddedsw

2023.2

https://github.com/Xilinx/embeddedsw/blob/xlnx_rel_v2023.2/doc/ChangeLog#L318

2023.1

• None

2022.2

• None

2022.1

• None

2021.2

• None

2021.1

https://github.com/Xilinx/embeddedsw/blob/xilinx_v2021.1/doc/ChangeLog#L356

2020.2

https://github.com/Xilinx/embeddedsw/blob/xilinx-v2020.2/doc/ChangeLog#L718

2020.1

https://github.com/Xilinx/embeddedsw/blob/xilinx-v2020.1/doc/ChangeLog#L232

2019.1

https://github.com/Xilinx/embeddedsw/blob/xilinx-v2019.2/doc/ChangeLog#L548

2017.1

https://github.com/Xilinx/embeddedsw/blob/xilinx-v2017.1/doc/ChangeLog#L1647

2016.1

https://github.com/Xilinx/embeddedsw/blob/xilinx-v2016.1/doc/ChangeLog#L391

Related Links

• http://www.wiki.xilinx.com/Baremetal+Drivers+and+Libraries