Table of Contents
IntroductionThis page gives an overview of axi performance monitor driver which is available as part of the Xilinx Vivado and SDK distribution.
The source code for the driver is included with the Vitis Unified Software Platform installation, as well as being available in the Xilinx Github repository.
The driver source code is organized into different folders. The table below shows the ipipsu driver source organization.
Provides the API and data structure details
Driver .tcl and .mdd file
Example applications that show how to use the driver features
Driver source files
For a full list of features supported by this IP, please refer Chapter 73: Octal SPI Controller in Versal TRM
- Connects as a 32-bit slave on AXI4-Lite interface
- Supports configurable ports.
- Supports configurable port sources.
- Supports configurable filters
- If you are using a old application then you can add the xil_macroback.h header file to the example and compile.
Refer to the driver examples directory for various example applications that exercise the different features of the driver. Each application is linked in the table below. The following sections describe the usage and expected output of the various applications. These example applications can be imported into the Vitis IDE from the Board Support Package settings tab.
Links to Examples
Example Application Usage
Pmonpsv self test example
Pmonpsv is used to monitor a sample access
WriteRequestValue: 0 WriteRespValue:0
Successfully ran PmonPsv selftest Example