This page gives an overview of the bare-metal driver support for the Xilinx® LogiCORE™ IP AXI USB soft IP. 

Table of Contents

Introduction

The AXI USB device IP is a USB device controller IP. It has no support for OTG mode. This IP can be instantiated on FPGA or Zynq or ZynqMP PL. This page describes the usage of AXI USB device IP standalone driver.
https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/usb/

Driver Sources

The source code for the driver is included with the Vitis Unified Software Platform installation and being available in the Xilinx Github repository. 

Note: To view the sources for a particular release, use the rel-version tag in Github.  For example, for the 2020.1 release, the proper version of the code is: https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/usb/

The driver source code is organized into different folders.  The table below shows the USB driver source organization. 

Note: AMD Xilinx embeddedsw build flow has been changed from 2023.2 release to adapt to the new system device tree based flow. For further information, refer to the wiki page Porting embeddedsw components to system device tree (SDT) based flow - Xilinx Wiki - Confluence (atlassian.net).

The .yaml(in data folder) and CMakeLists.txt(in src folder) files are needed for the System Device Tree based flow. The Driver .tcl and .mdd files are for the older build flow which will be deprecated in future.

Driver Implementation

For a full list of features supported by this IP,

Axi-USB: https://www.xilinx.com/products/intellectual-property/axi_usb2_device.html

Link: https://www.xilinx.com/support/documentation/ip_documentation/axi_usb2_device/v5_0/pg137-axi-usb2-device.pdf

Features Supported

Controller Features Supported

• USB 2.0 HS and FS Device controller.

• USB 1.1 legacy FS/LS.

• Local DMA Engine.

Driver Features Supported

• Support device mode only

Known Issues and Limitations

• Host mode is not supported

• OTG mode is not supported

Example Applications

Refer to the driver examples directory for various example applications that exercise the different features of the driver. Each application is linked in the table below. The following sections describe the usage and expected output of the various applications.  These example applications can be imported into the Vitis IDE from the Board Support Package settings tab. 

Links to Examples

Examples Path:
https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/usb/examples

Example Application Usage

Mass-Storage: USB Polled/Interrupt mode example

https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/usb/examples

Mass storage profile can be tested by compiling xusb_storage_polled_mode.c,xusb_cp9.c,xusb_cp9.h,xusb_storage.h,xusb_types.h and

https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/usb/src

xusb.h , xusb.c ,xusb_l.h
files together

USB 2.0 Peripheral Mode

The below gives the testing procedure of axi-usb device standalone example which operates as a mass storage gadget

Testing procedure

Mass storage profile can be tested by compiling files found in the below link

https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/usb/examples

Below is the testing procedure of AXI USB standalone example which operates as a mass storage gadget

• Download and run the generated USB 2.0 example ELF

• Connect board setup to standard host(Windows/Linux)machine USB 2.0 port.

Expected Output

• You will get a pop-up window on a Windows machine for formatting the size 256MB. After the format completes, you can copy the file to the USB device.

• Open

  

Example Design Architecture

AXI-USB specific design. This is the customized image of axi-usb and canfd. AXI Interconnect module connected with ULPI.

Open

Performance

The below performance results are observed using CrystalDiskMark tool on windows

Change Log

2024.1

• None

2023.2

https://github.com/Xilinx/embeddedsw/blob/xlnx_rel_v2023.2/doc/ChangeLog#L315

2023.1

• None

2022.2

• None

2022.1

• None

2021.2

• None

2021.1

https://github.com/Xilinx/embeddedsw/blob/xilinx_v2021.1/doc/ChangeLog#L2220

2020.2

https://github.com/Xilinx/embeddedsw/blob/xilinx-v2020.2/doc/ChangeLog#L715

2020.1

https://github.com/Xilinx/embeddedsw/blob/xilinx-v2020.1/doc/ChangeLog#L557

2016.2

https://github.com/Xilinx/embeddedsw/blob/xilinx-v2016.2/doc/ChangeLog#L43

2016.1

https://github.com/Xilinx/embeddedsw/blob/xilinx-v2016.1/doc/ChangeLog#L387

Related Links

• http://www.wiki.xilinx.com/Baremetal+Drivers+and+Libraries