Table of Contents

Introduction

This page gives an overview of zdma driver which is available as part of the Xilinx Vivado and Vitis distribution. ZDMA is a general purpose DMA designed to support memory to memory and memory to IO buffer transfers.

Zynq Ultrascale+ MPSOC has two instance of general purpose ZDMA.
One is located in FPD (full power domain) which usually called as GDMA and other is located in LPD (low power domain) which usually called as ADMA.

Versal has one instance of general purpose DMA in LPD (low power domain) known as ADMA.

For more information, please refer to ADMA/GDMA chapter in ZynqMP TRM (UG1085) or Versal TRM (AM011).

Driver Sources

The source code for the driver is included with the Vitis Unified Software Platform installation, as well as being available in the Xilinx Github repository. 

The driver source code is organized into different folders.  The table below shows the ZDMA driver source organization. 

Note: AMD Xilinx embeddedsw build flow is changed from 2023.2 release to adapt to the new system device tree based flow. For further information, refer to the wiki page Porting embeddedsw components to system device tree (SDT) based flow - Xilinx Wiki - Confluence (atlassian.net).

The .yaml(in data folder) and CMakeLists.txt(in src folder) files are needed for the System Device Tree based flow. The Driver .tcl and .mdd files are for the older build flow which will be deprecated in the future.

Driver Implementation

For a full list of features supported by this IP, please refer to ADMA/GDMA chapter in ZynqMP TRM (UG1085) or Versal TRM (AM011) for respective devices.

Features

Controller/Driver features supported

• GMDA & ADMA are configured each with 8 DMA channels and and each channel can be programmed secure or non-secure.

• It support two DMA Modes

  • Simple DMA mode

    • Normal data transfer from source to destination

    • Write Only Mode

    • Read Only Mode

  • Scatter Gather DMA mode

    • Normal data transfer from source to destination

• In Scatter gather Mode it supports 2 types of descriptors out of 3 that h/w supports

  • Linear descriptor

  • Linked list descriptor

• Interrupt Accounting Support

• INCR and Fixed burst are supported.

Known Issues and Limitations

• Hybrid list descriptors are not supported.

• Flow controller feature is not supported

• Peripheral DMA is not tested/supported.

Example Design Architecture

ZDMA examples demonstrate ZDMA features in simple and SG modes.

Example Applications

ZDMA driver supports a interrupt examples in various operating modes describing how its different features can be exercised. These example applications can be imported into the Vitis IDE from the Board Support Package settings tab. 

Links to Examples

Examples Path:
https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/zdma/examples

Example Application Usage

ZDMA Selftest example

Basic ZDMA selftest example to check sanity and use core APIs.

Expected Output

Successfully ran ZDMA Selftest Example

ZDMA Write-only example

ZDMA example demonstrating write-only feature.

Expected Output

Successfully ran Write Only mode ZDMA Example

ZDMA Read-only example

ZDMA example demonstrating read-only feature.

Expected Output

Successfully ran ZDMA Read Only Example

ZDMA SG Linear example

ZDMA example demonstrating Scatter Gather Linear descriptor mode.

Expected Output

Successfully ran ZDMA Linear mode Example

ZDMA SG Linked list example

ZDMA example demonstrating Scatter Gather Linked list descriptor mode.

Expected Output

Successfully ran ZDMA Linked list Example

ZDMA Simple DMA example

ZDMA example demonstrating Simple DMA mode.

Expected Output

Successfully ran ZDMA Simple Example

Performance

NA

Change Log

2024.1

https://github.com/Xilinx/embeddedsw/blob/xilinx_v2024.1/doc/ChangeLog#L386

2023.2

https://github.com/Xilinx/embeddedsw/blob/xlnx_rel_v2023.2/doc/ChangeLog#L567

2023.1

https://github.com/Xilinx/embeddedsw/blob/xilinx_v2023.1/doc/ChangeLog#L162

2022.2

https://github.com/Xilinx/embeddedsw/blob/xilinx_v2022.2/doc/ChangeLog#L206

2022.1

https://github.com/Xilinx/embeddedsw/blob/xilinx_v2022.1/doc/ChangeLog#L265

2021.2

https://github.com/Xilinx/embeddedsw/blob/xlnx_rel_v2021.2/doc/ChangeLog#L133

2021.1

https://github.com/Xilinx/embeddedsw/blob/xilinx_v2021.1/doc/ChangeLog#L326

2020.2

https://github.com/Xilinx/embeddedsw/blob/release-2020.2/doc/ChangeLog#L234

2020.1

No functional changes

https://github.com/Xilinx/embeddedsw/blob/release-2020.1/doc/ChangeLog#L569

2019.2

https://github.com/Xilinx/embeddedsw/blob/release-2019.2/doc/ChangeLog#L93

2019.1

https://github.com/Xilinx/embeddedsw/blob/release-2019.1/doc/ChangeLog#L290

2018.3

https://github.com/Xilinx/embeddedsw/blob/release-2018.3/doc/ChangeLog#L419

2018.2

None

2018.1

https://github.com/Xilinx/embeddedsw/blob/release-2018.1/doc/ChangeLog#L287

Related Links

• http://www.wiki.xilinx.com/Baremetal+Drivers+and+Libraries