Table of Contents
This page gives an overview of Root Port and Endpoint driver for the controller for PSU PCI Express, which is available as part of Xilinx Vivado and SDK distribution.
Source path for the driver:
Driver source code is organized into different folders. Below diagram shows the pciepsu driver source organization
├── data: Driver tcl and MDD files.
├── examples: Reference application to show how to use the driver APIs and calling sequence
└── src: Driver source files
Controller Features Supported
- Support for Gen1 (2.5 GT/s) or Gen2 (5.0 GT/s) link rates.
- Support for single x1, x2, or x4 link.
- Multiple Vector Messaged Signaled Interrupts (MSIs)
- Single Vector Messaged Signaled Interrupts
- Legacy PCI interrupt support
- Detects and indicates error conditions with interrupts
Standalone Driver Supported Features
- Initialize a PS PCIe root complex
- Enumerate PCIe end points in the system
- Assign BARs to endpoints
- Find capablities on end point
- Initialize PS PCIe endpoint
- Provides interface for Ingress translation for the Endpoint based on BAR address assigned by the Root Complex
- Refer below path for testing different examples for each feature of the IP
Known issues and Limitations
- Adds initial driver for PSU PCIe End Point.
- Adds initial driver for PSU PCIe Root complex.