Table of Contents

Introduction

This page gives an overview of Root Port driver for the PCIe controllers of  UltraScale+/Versal devices, which is available as part of Xilinx Vivado and Vitis distribution.

Source path for the driver:
https://github.com/Xilinx/embeddedsw/tree/release-2019.1/XilinxProcessorIPLib/drivers/xdmapcie

Driver source code is organized into different folders. Below diagram shows the driver source organization

xdmapcie

├── data: Driver tcl and MDD files. 
├── examples:  Reference application to show how to use the driver APIs and calling sequence
└── src: Driver source files

US+ Controller Features Supported

• Support for Gen1 (2.5 GT/s) or Gen2 (5.0 GT/s) or Gen3 (8.0 GT/s) link rates.

• Support for single x1, x2, x4 or x8 link.

• AXI Bridge for PCIe Gen3 supports UltraScale PCI Express

• DMA/Bridge Subsystem for PCI Express in AXI Bridge mode supports UltraScale+ Integrated Blocks for PCI Express

• Multiple Vector Messaged Signaled Interrupts (MSIs)

• Single Vector Messaged Signaled Interrupts

• Legacy PCI interrupt support

• Detects and indicates error conditions with interrupts

Standalone Driver Supported Features for US+ devices

• Initializes XDMA PCIe IP core built as a root complex

• Enumerate PCIe Endpoints in the system

• Assign BARs to Endpoints

• Finds Capabilities of the Endpoints

Versal Adaptive SoC Controller Features Supported

CPM4

• Support for Gen1 (2.5 GT/s) or Gen2 (5.0 GT/s) or Gen3 (8.0 GT/s) or Gen4 (16 GT/s) link rates.

• Support for single x1, x2, x4 or x8 or x16 link.

• Multiple Vector Messaged Signaled Interrupts (MSIs)

• Single Vector Messaged Signaled Interrupts

• Legacy PCI interrupt support

• Detects and indicates error conditions with interrupts

• Versal CCIX PCIe module(CPM) support for Root Complex. 

CPM5

• Support for Gen1 (2.5 GT/s) or Gen2 (5.0 GT/s) or Gen3 (8.0 GT/s) or Gen4 (16 GT/s) or Gen5 (32 GT/s) link rates.

• Support for single x1, x2, x4 or x8 link.

• Multiple Vector Messaged Signaled Interrupts (MSIs)

• Single Vector Messaged Signaled Interrupts

• Legacy PCI interrupt support

• Detects and indicates error conditions with interrupts

• Versal CCIX PCIe module(CPM) support for Root Complex. 

Versal Adaptive SoC Controller QDMA PL PCIe Features Supported

QDMA PL PCIe4 (Versal prime)

• Support for Gen1 (2.5 GT/s) or Gen2 (5.0 GT/s) or Gen3 (8.0 GT/s) or Gen4 (16 GT/s) link rates.

• Versal PL PCIe4 support for Root Complex.

• Legacy PCI interrupt support.

• Detects and indicates error conditions with interrupts

QDMA PL PCIe5 (Versal premium)

• Support for Gen1 (2.5 GT/s) or Gen2 (5.0 GT/s) or Gen3 (8.0 GT/s) or Gen4 (16 GT/s) or Gen5 (32 GT/s) link rates.

• Versal PL PCIe5 support for Root Complex.

• Legacy PCI interrupt support.

• Detects and indicates error conditions with interrupts

Standalone Driver Supported Features for Versal Adaptive SoC devices

• Initializes any of below IPs built as a root complex
  
  

  • Versal CPM PCIeA(refer AR76664)

  • Versal PL PCIe4

  • QDMA PL PCIE4(refer AR76665)

• Enumerate PCIe Endpoints in the system

• Assign BARs to Endpoints

• Finds Capabilities of the Endpoints

Test cases

• Refer below path for testing different examples for each feature of the IP

  • xdmapcie-examples

• xdmapcie_rc_enumerate_example.c : This example demonstrates how to use driver APIs which configures XDMA PCIe root complex.

Debugging information

• If Link is Down

  • Check if FSBL/boot firmware is downloaded into the board.

  • Check if EP is connected properly.

  • If using a switch, check if switch settings for the slot are correct or not. Try changing switch slots

  • Try changing EP device

  • Ensure you are using updated design/fsbl/boot firmware

• Endpoint not detected/enumerated

  • Try using a different endpoint device.

  • If using a switch, check if switch settings for the slot are correct or not. Try changing switch slots

• Ensure that tcl parses parameter correctly from the design.

  • This can be checked by getting the list of parameters from tcl file and matching corresponding values in xparameters.h with the one in design.
    For eg; in xdmapcie code, xdmapcie.tcl parses below attributes for peripheral psv_pciea_attrib_0:
    NUM_INSTANCES, DEVICE_ID, C_NOCPSPCIE0_REGION0, C_CPM_PCIE0_AXIBAR_NUM, C_CPM_PCIE0_PF0_AXIBAR2PCIE_HIGHADDR_0,
    C_CPM_PCIE0_PF0_AXIBAR2PCIE_BASEADDR_0, C_CPM_PCIE0_PF0_AXIBAR2PCIE_HIGHADDR_1, C_CPM_PCIE0_PF0_AXIBAR2PC.

• The driver has prints for error handling scenarios. Searching for error string in src/example code will give an hint.

• No prints shown

  • For PL based PCIe controllers, check if bitstream also downloaded

  • Ensure using a correct design

  • Try reading bridge base address through xsct/xsdb console and see if it works.

• In case any of above doesn’t work and if issue still persist raise support request along
  giving the below log:

  • The console prints

  • The Platform used with Endpoint and Switch details.

  • Version of xsdk/Vitis used

  • The design file

  • Boot images used

Known issues and Limitations

1. For support of Versal QDMA PL-PCIE4 as Root Complex, refer the procedure listed in AR76665

2. For support of Versal CPM 2021.1 designs as Root Complex, refer the steps listed in AR76664

Change Log

2021.1

• Added support for Versal QDMA PL-PCIE4 as Root Complex

2020.2

• Added support for Versal PL-PCIE4 as Root Complex

2019.2

• Added support for Versal CPM as Root Complex

2019.1

• Adds initial driver for XDMA PCIe Root complex.