IntroductionThis page gives an overview of UARTLite driver which is available as part of the Xilinx Vivado and SDK distribution.The LogiCORE™ IP AXI Universal Asynchronous Receiver Transmitter (UART) Lite core provides between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI interface and also provides a controller interface for asynchronous serial data transfer. This soft LogiCORE™ IP core is designed to interface with the AXI4-Lite protocol.Source path for the driver:https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/uartliteDriver source code is organized into different folders. Below diagram shows the iicps driver source organizationuartlite|-- Doc - Provides the API and data structure details|- Examples - Reference application to show how to use the driver APIs and calling sequence|- Source - Driver source files
Controller Features Supported:
• AXI4-Lite interface for register access and data transfers
• Full duplex
• 16-character transmit and receive FIFOs
• Configurable number of data bits (5-8) in a character
• Configurable parity bit (odd or even or none)
• Configurable baud rate
Driver Supported FeaturesThe UARTLite Standalone driver support the below things.All Controller Features supported.
Known issues and Limitations
Test casesRefer below pah for testing different examples for each feature of the IP.https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/uartlite/examples
- uartlite: Added xil_printf statement in examples.
- uartlite: Updated makefile.
- uartlite: Added readme.txt file to generate doxygen for examples
- 161c1b8 uartlite: Added xil_printf statement in examples.
- 4ba7f29 uartlite: Updated makefile.
- c3c4385 uartlite: Added readme.txt file to generate doxygen for examples
- drivers: Fix makefiles issue for windows