IntroductionThis page gives an overview of UARTLite driver which is available as part of the Xilinx Vivado and SDK distribution.The LogiCORE™ IP AXI Universal Asynchronous Receiver Transmitter (UART) Lite core provides between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI interface and also provides a controller interface for asynchronous serial data transfer. This soft LogiCORE™ IP core is designed to interface with the AXI4-Lite protocol.
The source code for the driver is included with the Vitis Unified Software Platform installation, as well as being available in the Xilinx Github repository.
The driver source code is organized into different folders. The table below shows the uartlite driver source organization.
• AXI4-Lite interface for register access and data transfers
• Full duplex
• 16-character transmit and receive FIFOs
• Configurable number of data bits (5-8) in a character
• Configurable parity bit (odd or even or none)
• Configurable baud rate
Known Issues and Limitations
Refer to the driver examples directory for various example applications that exercise the different features of the driver. Each application is linked in the table below. The following sections describe the usage and expected output of the various applications. These example applications can be imported into the Vitis IDE from the Board Support Package settings tab.
Links to Examples
Example Application Usage
Uartlite interrupt example
This example sends and receives data using interrupts.
Successfully ran Uartlite interrupt Example
Uartlite polled example
This example sends and receives data using polling.
Successfully ran Uartlite polled Example
Uartlite tapp interrupt example
This example just transmits the data using interrupts.
Successfully ran Uartlite interrupt tapp Example
Example Design Architecture