AXI UART Lite standalone driver
- Confluence Wiki Admin (Unlicensed)
- Alvin Paul P
- Manikanta Guntupalli
This page gives an overview of UARTLite BareMetal driver which is available as part of the Xilinx Vivado and SDK distribution.
Table of Contents
Introduction
The LogiCORE™ IP AXI Universal Asynchronous Receiver Transmitter (UART) Lite core provides between
UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI interface and also provides
a controller interface for asynchronous serial data transfer. This soft LogiCORE™ IP core is designed to
interface with the AXI4-Lite protocol.
Driver Sources
The source code for the driver is included with the Vitis Unified Software Platform installation, as well as being available in the Xilinx Github repository.
| Driver name | Path in vitis | Path in github |
|---|---|---|
| uartlite | <Vitis Install Directory>/data/embedded/XilinxProcessorIPLib/drivers/uartlite | https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/uartlite |
Note: To view the sources for a particular release, use the rel-version tag in github. For example, for the 2020.1 release, the proper version of the code is: https://github.com/Xilinx/embeddedsw/tree/xilinx-v2020.1/XilinxProcessorIPLib/drivers/uartlite
The driver source code is organized into different folders. The table below shows the uartlite driver source organization.
Directory | Description |
|---|---|
doc | Provides the API and data structure details |
data | Driver .tcl, .yaml and .mdd file |
examples | Example applications that show how to use the driver features |
| src | Driver source files, make and cmakelists file |
Note: AMD Xilinx embeddedsw build flow has been changed from 2023.2 release to adapt to the new system device tree based flow. For further information, refer to the wiki link Porting embeddedsw components to system device tree (SDT) based flow
The .yaml(in data folder) and CMakeLists.txt(in src folder) files are needed for the System Device Tree based flow. The Driver .tcl and .mdd files are for the older build flow which will be deprecated in future.
Driver Implementation
For a full list of features supported by this IP, please refer https://www.xilinx.com/support/documentation/ip_documentation/axi_uartlite/v2_0/pg142-axi-uartlite.pdf
Features
• AXI4-Lite interface for register access and data transfers• Full duplex
• 16-character transmit and receive FIFOs
• Configurable number of data bits (5-8) in a character
• Configurable parity bit (odd or even or none)
• Configurable baud rate
Known Issues and Limitations
None
Example Applications
Refer to the driver examples directory for various example applications that exercise the different features of the driver. Each application is linked in the table below. The following sections describe the usage and expected output of the various applications. These example applications can be imported into the Vitis IDE from the Board Support Package settings tab.
Links to Examples
Examples Path:
https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/uartlite/examples
| Test Name | Example Source | Description |
|---|---|---|
| Uartlite interrupt example | xuartlite_intr_example.c | This example sends and receives data using interrupts. |
| Uartlite polled example | xuartlite_polled_example.c | This example sends and receives data using polling. |
| Uartlite tapp interrupt example | xuartlite_intr_tapp_example.c | This example just transmits the data using interrupts. |
Uartlite selftest_example | xuartlite_selftest_example.c | This example performs the basic selftest using the driver. |
Uartlite low_level_example | xuartlite_low_level_example.c | This example shows the usage of the low-level driver functions and macros of the driver. |
Example Application Usage
Uartlite interrupt example
This example sends and receives data using interrupts.Successfully ran Uartlite interrupt Example
Uartlite polled example
This example sends and receives data using polling.
Expected Output
Successfully ran Uartlite polled Example
Uartlite tapp interrupt example
This example just transmits the data using interrupts.Successfully ran Uartlite interrupt tapp Example
Example Design Architecture
NA
Change Log
2024.1
https://github.com/Xilinx/embeddedsw/blob/xlnx_rel_v2024.1/doc/ChangeLog#L930
2023.2
https://github.com/Xilinx/embeddedsw/blob/xlnx_rel_v2023.2/doc/ChangeLog#L125
2023.1
https://github.com/Xilinx/embeddedsw/blob/xilinx_v2023.1/doc/ChangeLog#L138
2022.2
None
2022.1
https://github.com/Xilinx/embeddedsw/blob/xilinx_v2022.1/doc/ChangeLog#L119
2021.2
None
2021.1
https://github.com/Xilinx/embeddedsw/blob/xilinx_v2021.1/doc/ChangeLog#L483
2020.2
None
2020.1
None
2019.2
None
2019.1
None
2018.3
None
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