Mbox

This page gives an overview of mailbox driver which is available as part of the Xilinx Vivado and SDK distribution.

Table of Contents


Introduction

In a multiprocessor environment, the processors need to communicate data with each other. The easiest method is to set up inter-processor communication through a mailbox. The Mailbox core features a bidirectional communication channel between two processors

Driver Sources

The source code for the driver is included with the Vitis Unified Software Platform installation, as well as being available in the Xilinx Github repository. 

Driver Name

Path in Vitis

Path in Github

mbox

<Vitis Install Directory>/data/embedded/XilinxProcessorIPLib/drivers/mbox

https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/mbox

Note: To view the sources for a particular release, use the rel-version tag in github.  For example, for the 2020.1 release, the proper version of the code is: https://github.com/Xilinx/embeddedsw/tree/xilinx-v2020.1/XilinxProcessorIPLib/drivers/mbox

The driver source code is organized into different folders.  The table below shows the mbox driver source organization. 

Directory
Description

doc

Provides the API and data structure details

data

Driver .tcl , .mdd and .yaml files

examples

Example applications that show how to use the driver features

src

Driver source files, make and cmakelists file

Note: AMD Xilinx embeddedsw build flow is changed from 2023.2 release to adapt to the new system device tree based flow. For further information, refer to the wiki page Porting embeddedsw components to system device tree (SDT) based flow - Xilinx Wiki - Confluence (atlassian.net).

The .yaml(in data folder) and CMakeLists.txt(in src folder) files are needed for the System Device Tree based flow. The Driver .tcl and .mdd files are for the older build flow which will be deprecated in the future.

Driver Implementation

For a full list of features supported by this IP, Versal TRM

Features

  1. Supports AXI4-Lite and AXI4-Stream independently on each of the ports
  2. Configurable depth of mailbox
  3. Configurable interrupt thresholds and maskable interrupts
  4. Configurable synchronous or asynchronous operation
  5. Bidirectional communication

Example Applications

Refer to the driver examples directory for various example applications that exercise the different features of the driver. Each application is linked in the table below. The following sections describe the usage and expected output of the various applications.  These example applications can be imported into the Vitis IDE from the Board Support Package  settings tab. 

Links to Examples

Examples Path:
https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/mbox/examples

Test Name

Example Source

Description
Mbox Polled mode example

xmbox_example.c


It is a simple example of initializing the core and passing data from one processor to another
Mbox Interrupt mode example

xmbox_intr_example.c


It is a simple example of initializing the core and passing data from one processor to another in interrupt mode.
Mbox Tapp examplexmbox_tapp_example.cIt is a simple example of initializing the core and passing data from one processor to another processor. If Mailbox is connected to only one
Processor then Data has to be sent from one port and should be received from another port.

Example Application Usage

Mbox Polled mode example

It is a simple example of initializing the core and passing data from one processor to another

Expected Output

Mbox Interrupt mode example


It is a simple example of initializing the core and passing data from one processor to another in interrupt mode


Expected Output

Mbox Tapp example


It is a simple example of initializing the core and passing data from one processor to another processor. If Mailbox is connected to only one
Processor then Data has to be sent from one port and should be received from another port.


Expected Output

Change log

2024.1

2023.2


2023.1

  • None

2022.2

  • None

2022.1

  • None

2021.1

  • None

2020.2

  • None

2020.1

  • None

2019.2

  • None

2019.1

  • None

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