This page gives an overview of mailbox driver which is available as part of the Xilinx Vivado and SDK distribution.
Table of Contents
The source code for the driver is included with the Vitis Unified Software Platform installation, as well as being available in the Xilinx Github repository.
The driver source code is organized into different folders. The table below shows the ospipsv driver source organization.
Provides the API and data structure details
Driver .tcl and .mdd file
Example applications that show how to use the driver features
Driver source files
For a full list of features supported by this IP, Versal TRM
- Supports AXI4-Lite and AXI4-Stream independently on each of the ports
- Configurable depth of mailbox
- Configurable interrupt thresholds and maskable interrupts
- Configurable synchronous or asynchronous operation
- Bidirectional communication
Refer to the driver examples directory for various example applications that exercise the different features of the driver. Each application is linked in the table below. The following sections describe the usage and expected output of the various applications. These example applications can be imported into the Vitis IDE from the Board Support Package settings tab.
Links to Examples
|Mbox Polled mode example|
|It is a simple example of initializing the core and passing data from one processor to another|
|Mbox Interrupt mode example|
|It is a simple example of initializing the core and passing data from one processor to another in interrupt mode..|
Example Application Usage
Mbox Polled mode example
It is a simple example of initializing the core and passing data from one processor to another
Mbox Interrupt mode example
It is a simple example of initializing the core and passing data from one processor to another in interrupt mode