This page gives an overview of the bare-metal driver support for the Versal SbSa UART

Table of Contents

Introduction

The UART controller is a full-duplex asynchronous receiver and transmitter that supports a wide range of programmable baud rates. The server-based system applications (SBSA) functionality is defined by the Arm® architecture. There are two UART controllers, and they are located in the LPD IOP. The UART performs the following: • Serial-to-parallel conversion on data received from a peripheral device • Parallel-to-serial conversion on data transmitted to a peripheral device The software performs reads and writes of data and control/status information via the APB slave interface.

Driver Sources

The source code for the driver is included with the Vitis Unified Software Platform installation, as well as being available in the Xilinx Github repository. 

Note: To view the sources for a particular release, use the rel-version tag in github.  For example, for the 2020.1 release, the proper version of the code is: https://github.com/Xilinx/embeddedsw/tree/xilinx-v2020.1/XilinxProcessorIPLib/drivers/uartpsv

The driver source code is organized into different folders.  The table below shows the uartpsv driver source organization. 

Note: AMD Xilinx embeddedsw build flow has been changed from 2023.2 release to adapt to the new system device tree based flow. For further information, refer to the wiki link Porting embeddedsw components to system device tree (SDT) based flow
The .yaml(in data folder) and CMakeLists.txt(in src folder) files are needed for the System Device Tree based flow. The Driver .tcl and .mdd files are for the older build flow which will be deprecated in future.

Driver Implementation

For a full list of features supported by this IP, please refer Versal TRM

Features

32 deep ×8-bit wide transmit FIFO

32 deep ×12-bit wide receive FIFO

Standard asynchronous communication bits (start, stop and parity)

Independent interrupt masking

Programmable hardware flow control

Fully-programmable serial interface characteristics

FIFO trigger levels selectable between 1/8, 1/4, 1/2, 3/4, and 7/8

Known Issues and Limitations

• None

Example Applications

Refer to the driver examples directory for various example applications that exercise the different features of the driver. Each application is linked in the table below. The following sections describe the usage and expected output of the various applications.  These example applications can be imported into the Vitis IDE from the Board Support Package  settings tab. 

Links to Examples

Examples Path:
https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/ospipsv/examples

Example Application Usage

Refer to the driver examples directory for various example applications that exercise the different features of the driver. Each application is linked in the table below. The following sections describe the usage and expected output of the various applications.  These example applications can be imported into the Vitis IDE from the Board Support Package  settings tab. 

Example Application Usage

Uartpsv interrupt example

This example sends and receives data using interrupts.

Expected Output

Uartpsv polled example

This example sends and receives data using polling.

Expected Output

Uartpsv hello world example

This example transmits “Hello world“ string

Expected Output

Example Design Architecture

NA

Change Log

2023.2

https://github.com/Xilinx/embeddedsw/blob/xlnx_rel_v2023.2/doc/ChangeLog#L147

2023.1

https://github.com/Xilinx/embeddedsw/blob/xilinx_v2023.1/doc/ChangeLog#L146

2022.2

None

2021.2

None

2021.1

https://github.com/Xilinx/embeddedsw/blob/xilinx_v2021.1/doc/ChangeLog#L353

2020.2

https://github.com/Xilinx/embeddedsw/blob/xilinx_v2021.1/doc/ChangeLog#L353

2020.1

https://github.com/Xilinx/embeddedsw/blob/xilinx-v2020.1/doc/ChangeLog#L136

2019.2

None

2019.1

None

Related Links

• http://www.wiki.xilinx.com/Baremetal+Drivers+and+Libraries