Nandps standalone driver

This page gives an overview of the bare-metal driver support for the Static Memory Controller (SMC).

Table of Contents

Introduction

The Static Memory Controller(SMC) can be used either as a NAND flash controller or a parallel port memory controller supporting the following memory types:
• NAND flash
• Asynchronous SRAM
• NOR flash

The operational registers of the SMC are configured through an APB interface. The SMC handles all commands, addresses, data, and the memory device protocols. It allows the users to access the controller by reading or writing into the operational registers. The SMC is based on Arm's PL353 static memory controller.

Driver Sources

The source code for the driver is included with the Vitis Unified Software Platform installation, as well as being available in the Xilinx Github repository.

Driver Name

Path in Vitis

Path in Github

nandps

<Vitis Install Directory>/data/embedded/XilinxProcessorIPLib/drivers/nandps

https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/nandps

Note: To view the sources for a particular release, use the rel-version tag in github.  For example, for the 2020.1 release, the proper version of the code is: https://github.com/Xilinx/embeddedsw/tree/xilinx-v2020.1/XilinxProcessorIPLib/drivers/nandps

The driver source code is organized into different folders.  The table below shows the nandps driver source organization.

Directory
Description

doc

Provides the API and data structure details

data

Driver .tcl,.mdd file and .yaml files

examples

Example applications that show how to use the driver features

src

Driver source files, make and cmake files

Note: AMD Xilinx embeddedsw build flow is changed from 2023.2 release to adapt to the new system device tree based flow. For further information, refer to the wiki page Porting embeddedsw components to system device tree (SDT) based flow - Xilinx Wiki - Confluence (atlassian.net).

The .yaml(in data folder) and CMakeLists.txt(in src folder) files are needed for the System Device Tree based flow. The Driver .tcl and .mdd files are for the older build flow which will be deprecated in the future.

Driver Implementation

For a full list of features supported by this IP, please refer Chapter 11: Static Memory Controller in Zynq TRM.

Features

  1. ONFI 1.0 compatible
  2. upto 1GB device
  3. 8/16-bit IO width with a single chip select
  4. 16-word read/write FIFOs
  5. 8-word command FIFO
  6. Programmable IO Cycle timing
  7. 1-bit ECC hardware with sw assist
  8. Asynchronous memory operating mode
  9. Supports only the mandatory ONFI 1.0 commands. i.e Reset, Read status, Read ID, Read Parameter Page, Read Page, Program Page, Erase Block, Set/Get Features
  10. supports page cache read operations
  11. Support BBT management
  12. Support for ondie ecc devices

Known issues and Limitations

  • Driver supports polled mode only
  • No support for interleaved and optional 1.0 commands

Supported Flash vendors

  • Micron

Example Applications

Refer to the driver examples directory for various example applications that exercise the different features of the driver. Each application is linked in the table below. The following sections describe the usage and expected output of the various applications.  These example applications can be imported into the Vitis IDE from the Board Support Package  settings tab

Links to Examples

Examples Path:

https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/nandps/examples

Test NameExample SourceDescription
NANDPS Examplexnandps_example.chis examples does basic read and write test from the NAND flash device
NANDPS Cache Examplexnandps_cache_example.cThis example tests Page cache read & write command on NAND Flash Device.
NANDPS Skip Block Examplexnandps_skip_example.cThis example tests the skip block method of erase/read/write operation on NAND Flash Device.

Example Application Usage

NANDPS Example

This examples does basic read and write test from the NAND flash device.

Nand Flash Read Write Example Test

Successfully ran Nand Flash Read Write Example Test

NANDPS Cache Example

This example tests Page cache read & write command on NAND Flash Device.

Nand Flash Read Write Example Test

Successfully ran Nand Flash Read Write Example Test

NANDPS Skip Block Example

This example tests the skip block method of erase/read/write operation on NAND Flash Device

Nand Flash Skip Block Method Example Test

Successfully ran Nand Flash Skip Block Method Example Test

Example Design Architecture

NA

Performance

Write(mbps)Read(mbps)
7.113.8

Change Log

2024.1

https://github.com/Xilinx/embeddedsw/blob/xlnx_rel_v2024.1/doc/ChangeLog#L485

2023.2

https://github.com/Xilinx/embeddedsw/blob/xlnx_rel_v2023.2/doc/ChangeLog#L709

2023.1

None

2022.2

None

2022.1

None

2021.2

None

2021.1

https://github.com/Xilinx/embeddedsw/blob/xilinx_v2021.1/doc/ChangeLog#L451

2020.2

https://github.com/Xilinx/embeddedsw/blob/xilinx-v2020.2/doc/ChangeLog#L633

2020.1

https://github.com/Xilinx/embeddedsw/blob/xilinx-v2020.1/doc/ChangeLog#L503

2019.2

https://github.com/Xilinx/embeddedsw/blob/xilinx-v2019.2/doc/ChangeLog#L1954

2019.1

https://github.com/Xilinx/embeddedsw/blob/xilinx-v2019.1/doc/ChangeLog#L1715



© Copyright 2019 - 2022 Xilinx Inc. Privacy Policy