This page gives an overview of the bare-metal driver support for the PS NAND Controller.

1 Introduction
2 Driver Sources
3 Driver Implementation
- 3.1 Features
- 3.2 Known Issues and Limitations
- 3.3 Supported Flash vendors
4 Example Applications
- 4.1 Links to Examples
- 4.2 Example Application Usage
  - 4.2.1 NAND Example
5 Example Design Architecture
6 Performance
7 Change Log
- 7.1 2025.2
- 7.2 2025.1
- 7.3 2024.2
- 7.4 2024.1
- 7.5 2023.2
- 7.6 2023.1
- 7.7 2022.2
- 7.8 2022.1
- 7.9 2021.2
- 7.10 2021.1
- 7.11 2020.2
- 7.12 2020.1
- 7.13 2019.2
- 7.14 2019.1
8 Related Links

Introduction

The NAND flash controller configuration and operational registers are programmed via its AXI slave interface. The block supports the open NAND flash interface working group (ONFI) standards 1.0, 2.0, 2.1, 2.2, 2.3, 3.0, and 3.1. The controller handles all the command, address, and data sequences, manages all the hardware protocols, and allows access NAND flash memory simply by reading or writing into the operational registers. The NAND DMA controller accesses system memory using its AXI master interface.

Driver Sources

The source code for the driver is included with the Vitis Unified Software Platform installation, as well as being available in the Xilinx Github repository.

Driver Name	Path in Vitis	Path in Github

Driver Name	Path in Vitis	Path in Github
nandpsu	<Vitis Install Directory>/data/embedded/XilinxProcessorIPLib/drivers/nandpsu	https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/nandpsu

Note: To view the sources for a particular release, use the rel-version tag in github. For example, for the 2020.1 release, the proper version of the code is: https://github.com/Xilinx/embeddedsw/tree/xilinx-v2020.1/XilinxProcessorIPLib/drivers/nandpsu

The driver source code is organized into different folders. The table below shows the nandpsu driver source organization.

Directory	Description

Directory	Description
doc	Provides the API and data structure details
data	Driver .tcl,.mdd file and .yaml files
examples	Example applications that show how to use the driver features
src	Driver source files, make and cmake files

Note: AMD Xilinx embeddedsw build flow is changed from 2023.2 release to adapt to the new system device tree based flow. For further information, refer to the wiki page Porting embeddedsw components to system device tree (SDT) based flow - Xilinx Wiki - Confluence (atlassian.net).

The .yaml(in data folder) and CMakeLists.txt(in src folder) files are needed for the System Device Tree based flow. The Driver .tcl and .mdd files are for the older build flow which will be deprecated in the future.

Driver Implementation

For a full list of features supported by this IP, please refer Chapter 25: NAND Memory Controller in ZynqMP TRM.

Features

Complies with the ONFI 3.1 specification
Supports interleaving operations
Supports BCH error correction code (ECC) data widths of 4, 8, 12, and 24 bits.
All ONFI 3.1 commands
PIO and MDMA support
SDR mode
supports only 8-bit bus support
Hardware ECC (Hamming code and BCH)
Page size up to 16K
Programmable timing modes
64-bit dma support.
Supports multiple chip selects (up to 2)

Known Issues and Limitations

Driver supports polled mode only
No support for interleaved and all optional ONFI 3.1 commands

Supported Flash vendors

Micron

Example Applications

Refer to the driver examples directory for various example applications that exercise the different features of the driver. Each application is linked in the table below. The following sections describe the usage and expected output of the various applications. These example applications can be imported into the Vitis IDE from the Board Support Package settings tab

Links to Examples

Examples Path:

https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/nandpsu/examples

Test Name	Example Souce	Description

Test Name	Example Souce	Description
NAND Example	xnandpsu_example.c	This examples does basic read and write test from the NAND flash device

Example Application Usage

NAND Example

This examples does basic read and write test from the NAND flash device.

^{Nand Flash Read Write Example Test

Manufacturer: MICRON MT29F32G08ABCDBJ4 ,

Device Model: MT29F32G08ABCDBJ4 ,

Jedec ID: 0x2C

Bytes Per Page: 0x4000

Spare Bytes Per Page: 0x4C0

Pages Per Block: 0x100

Blocks Per LUN: 0x418

Number of LUNs: 0x1

Number of bits per cell: 0x1

Number of ECC bits: 0xFF

Block Size: 0x400000

Number of Target Blocks: 0x418

Number of Target Pages: 0x41800

ECC: addr 0x4220 size 0x2A0 numbits 24 codesz 10

XNandPsu_ReadBbt: Bad block table not found

Successfully ran Nand Flash Read Write Example Test}

Example Design Architecture

NA

Performance

Timing Mode	Write(mbps)	Read(mbps)

Timing Mode	Write(mbps)	Read(mbps)
SDR mode 0	6.4	7.7
SDR mode 1	11.2	15.1
SDR mode 2	13.0	18.7
SDR mode 3	15.1	24.4
SDR mode 4	15.6	24.5
SDR mode 5	15.7	24.5
NVDDR mode 0	31.0	107.7
NVDDR mode 1	31.0	106.2
NVDDR mode 2	31.0	106.3
NVDDR mode 3	31.0	107
NVDDR mode 4	31.0	106.3
NVDDR mode 5	31.0	106.3