Nandpsu standalone driver

Introduction

This page gives an overview of nandpsu driver which is available as part of the Xilinx Vivado and SDK distribution.

Source path for the driver:
https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/nandpsu

Driver source code is organized into different folders. Below diagram shows the nandpsu driver source organization

nandpsu
|
-- Doc - Provides the API and data structure details
|
- Examples - Reference application to show how to use the driver APIs and calling sequence
|
- Source - Driver source files

Features Supported

Controller Features:

  • Complies with the ONFI 3.1 specification
  • Supports interleaving operations
  • Supports BCH error correction code (ECC) data widths of 4, 8, 12, and 24 bits.
  • All ONFI 3.1 commands
  • PIO and MDMA support
  • SDR and NVDDR modes
  • supports only 8-bit bus support
  • Hardware ECC (Hamming code and BCH)
  • Page size up to 16K
  • Programmable timing modes
  • 64-bit dma support.
  • Supports multiple chip selects (up to 2)

Driver Features:

  • Supports only the mandatory ONFI 3.1 commands. i.e Reset, Read status, Read ID, Read Parameter Page, Read Page, Program Page, Erase Block, Set/Get Features
  • Supports SDR/DDR modes
  • Supports timing modes 0-5
  • Supports PIO and MDMA support
  • Support for multiple chip selection
  • Support BBT management

Bad Block management

Bad block management implementation is same as Linux MTD bad block management with the exception of reserving number of blocks to store Bad Block Table (BBT) from default 4 blocks to 64 blocks. This is because one of the Micron flash part MT29F32G08ABCDB has last 32 blocks as bad most of the times. Since it was difficult to store bad block table in last 4 blocks, the number of blocks are increased to 64 blocks.

Known issues and Limitations

  • Driver supports polled mode only
  • No support for interleaved and all optional ONFI 3.1 commands

ChangeLog

  • 2016.3

    • Summary
      • None
    • Commits
      • None
  • 2016.4

    • Summary
      • None
    • Commits
      • None
  • 2017.1

    • Summary
      • Fix for reading nand redundant parameter pages
    • Commit id
  • 2017.2

    • Summary
      • None
    • Commits
      • None
  • 2017.3

    • Summary
      • Added CCI support
    • Commit
  • 2017.4

    • Summary
      • None
    • Commits
      • None
  • 2018.1

    • Summary
      • None
    • Commits
      • None
  • 2018.2

    • Summary
      • None
    • Commits
      • None
  • 2018.3

    • Summary
      • Support 64 bit DMA addresses for Microblaze-X
    • Commit
  • 2019.1

    • Summary
      • None
    • Commits
      • None
  • 2019.2

    • Summary
      • None
    • Commits
      • None
  • 2020.1

    • Summary
      • Add clocking support
    • Commits
  • 2020.2

    • Summary
      • None
    • Commits
      • None

Test cases

Nandpsu example:

https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/nandpsu/examples/xnandpsu_example.c
It verifies the nand data integrity by programing the known data pattern and verify the same by reading the data back.
In this process erase, program, read, read ID, Read Parameter Page, Reset, read status, get/set features and bbt management are covered
Output:

Performance:

Timing ModeWrite(MBPS)Read(MBPS)
SDR mode 06.47.7
SDR mode 111.215.1
SDR mode 213.018.7
SDR mode 315.124.4
SDR mode 415.624.5
SDR mode 515.724.5
NVDDR mode 031.0107.7
NVDDR mode 131.0106.2
NVDDR mode 231.0106.3
NVDDR mode 331.0107
NVDDR mode 431.0106.3
NVDDR mode 531.0106.3

Related Links