Nandpsu standalone driver

This page gives an overview of the bare-metal driver support for the PS NAND Controller.

Table of Contents


The NAND flash controller configuration and operational registers are programmed via its AXI slave interface. The block supports the open NAND flash interface working group (ONFI) standards 1.0, 2.0, 2.1, 2.2, 2.3, 3.0, and 3.1. The controller handles all the command, address, and data sequences, manages all the hardware protocols, and allows access NAND flash memory simply by reading or writing into the operational registers. The NAND DMA controller accesses system memory using its AXI master interface.

Driver Sources

The source code for the driver is included with the Vitis Unified Software Platform installation, as well as being available in the Xilinx Github repository.

Driver Name

Path in Vitis

Path in Github


<Vitis Install Directory>/data/embedded/XilinxProcessorIPLib/drivers/nandpsu

Note: To view the sources for a particular release, use the rel-version tag in github.  For example, for the 2020.1 release, the proper version of the code is:

The driver source code is organized into different folders.  The table below shows the nandpsu driver source organization.



Provides the API and data structure details


Driver .tcl,.mdd file and .yaml files


Example applications that show how to use the driver features


Driver source files, make and cmake files

Note: AMD Xilinx embeddedsw build flow is changed from 2023.2 release to adapt to the new system device tree based flow. For further information, refer to the wiki page Porting embeddedsw components to system device tree (SDT) based flow - Xilinx Wiki - Confluence (

The .yaml(in data folder) and CMakeLists.txt(in src folder) files are needed for the System Device Tree based flow. The Driver .tcl and .mdd files are for the older build flow which will be deprecated in the future.

Driver Implementation

For a full list of features supported by this IP, please refer Chapter 25: NAND Memory Controller in ZynqMP TRM.


  1. Complies with the ONFI 3.1 specification
  2. Supports interleaving operations
  3. Supports BCH error correction code (ECC) data widths of 4, 8, 12, and 24 bits.
  4. All ONFI 3.1 commands
  5. PIO and MDMA support
  6. SDR mode
  7. supports only 8-bit bus support
  8. Hardware ECC (Hamming code and BCH)
  9. Page size up to 16K
  10. Programmable timing modes
  11. 64-bit dma support.
  12. Supports multiple chip selects (up to 2)

Known Issues and Limitations

  • Driver supports polled mode only
  • No support for interleaved and all optional ONFI 3.1 commands

Supported Flash vendors

  • Micron

Example Applications

Refer to the driver examples directory for various example applications that exercise the different features of the driver. Each application is linked in the table below. The following sections describe the usage and expected output of the various applications.  These example applications can be imported into the Vitis IDE from the Board Support Package  settings tab

Links to Examples

Examples Path:

Test NameExample SouceDescription
NAND Examplexnandpsu_example.cThis examples does basic read and write test from the NAND flash device

Example Application Usage

NAND Example

This examples does basic read and write test from the NAND flash device.

Nand Flash Read Write Example Test

Manufacturer: MICRON      MT29F32G08ABCDBJ4   ,

Device Model: MT29F32G08ABCDBJ4   ,

Jedec ID: 0x2C

Bytes Per Page: 0x4000

Spare Bytes Per Page: 0x4C0

Pages Per Block: 0x100

Blocks Per LUN: 0x418

Number of LUNs: 0x1

Number of bits per cell: 0x1

Number of ECC bits: 0xFF

Block Size: 0x400000

Number of Target Blocks: 0x418

Number of Target Pages: 0x41800

ECC: addr 0x4220 size 0x2A0 numbits 24 codesz 10

XNandPsu_ReadBbt: Bad block table not found

Successfully ran Nand Flash Read Write Example Test

Example Design Architecture



Timing ModeWrite(mbps)Read(mbps)
SDR mode 06.47.7
SDR mode 111.215.1
SDR mode 213.018.7
SDR mode 315.124.4
SDR mode 415.624.5
SDR mode 515.724.5
NVDDR mode 031.0107.7
NVDDR mode 131.0106.2
NVDDR mode 231.0106.3
NVDDR mode 331.0107
NVDDR mode 431.0106.3
NVDDR mode 531.0106.3

Change Log













© Copyright 2019 - 2022 Xilinx Inc. Privacy Policy