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SMPTE UHD‑SDI Receiver Standalone Driver

SMPTE UHD‑SDI Receiver Standalone Driver

Table of Contents

Introduction

Core and Driver supported features:

Test cases

1. Introduction

The SMPTE UHD‑SDI Receiver Subsystem (SDI RXSS) standalone driver provides a bare‑metal API and example applications to bring up and validate UHD‑SDI receive pipelines on AMD platforms. The driver targets SDI receive and pass‑through use cases and exposes control and status of the SDI RX and TX subsystems, including audio extraction/embedding, through a UART console.

The IP‑level architecture, feature set, and configuration options are described in PG290. This page focuses on the standalone driver view and the SDI pass‑through example.

2. Driver Features

  • Support for SMPTE UHD‑SDI receive capabilities across supported SDI standards (HD‑SDI, 3G‑SDI, 6G‑SDI, 12G‑SDI) as configured in the subsystem

  • Supports multi‑rate operation with automatic rate detection when enabled in the subsystem configuration

  • Supports SDI video formats including 720p, 1080i, 1080p, and UHD resolutions as defined in PG290 and within device bandwidth limits

  • Supports YCbCr 4:2:2 color format at 10 bits per component for standard UHD‑SDI streams, with additional color format support depending on subsystem configuration

  • Provides AXI4‑Stream video interfaces for integration with downstream video processing pipelines

  • Supports embedded SDI audio extraction from the incoming SDI stream

  • Supports SDI audio embedding into the outgoing SDI stream

  • Supports AES3 (SPDIF) audio capture and playback in conjunction with the SDI audio extract/embed paths

  • Provides status and control for input lock, SDI mode, frame format, and ST352 payload via register interface

  • Supports access to SDI RX and TX stream information (mode, resolution, frame rate, color format, pixel clock) from software

  • Integrates with AMD clocking and transceiver resources as described in PG290 for supported devices

For the complete and authoritative feature list, refer to the SMPTE UHD‑SDI Receiver Subsystem Product Guide (PG290):
https://docs.amd.com/r/en-US/pg290-v-smpte-uhdsdi-rx-ss?tocId=pKTtVCVd1WW2Yy11d~WkEQ

3. Implementation

The SDI RXSS standalone driver is delivered as part of the standard embeddedsw tree.

  • Driver name: typically xsdi_rxss / xv_sdi_rxss (per embeddedsw naming)

  • Typical repository path:
    XilinxProcessorIPLib/drivers/ (SDI RXSS driver folder)

3.1 Driver layering

The driver stack is organized as:

  • Core IP drivers

    • SDI RX core driver

    • SDI TX core driver (for pass‑through)

    • Audio extract and embed drivers

    • SPDIF (AES3) drivers
      These manage low‑level register access, mode configuration, and interrupt handling.

  • Subsystem / example driver layer

    • Wraps the UHD‑SDI Receiver Subsystem and associated SDI TX/audio IP

    • Provides initialization and configuration flows for RX, TX, audio extract, and audio embed blocks

    • Exposes APIs for stream info, lock status, audio group detection, and control of audio routing

  • Example applications

    • SDI Pass‑Through Example (provided in this page)

      • Video pass‑through from SDI RX to SDI TX

      • SDI audio pass‑through and AES3 capture/playback modes

      • UART menu to view status, logs, and debug information

During startup, the example initializes the SDI audio embed and extract driver, registers interrupt handlers for SPDIF RX/TX and SDI audio extract/embed, and then enters the main menu loop.

4. Known issues and limitations

For the SDI pass‑through standalone driver example:

  • There are no specific known issues for the basic SDI video and audio pass‑through flow corresponding to the reference log in Section 7.1.

  • The example is intended as a bring‑up and debug utility and focuses on:

    • Single‑link SDI video pass‑through

    • Embedded audio pass‑through and AES3 capture/playback

  • More advanced configurations (multi‑link UHD, additional color formats, proprietary modes) are dependent on the specific IP and board configuration and may require additional software or customization beyond this example.

Please refer to PG290 for supported device families, SDI standards, and any IP‑level limitations:
https://docs.amd.com/r/en-US/pg290-v-smpte-uhdsdi-rx-ss?tocId=pKTtVCVd1WW2Yy11d~WkEQ

5. Example applications

5.1 SDI pass‑through example

The SDI Pass Through Example is a standalone bare‑metal application that:

  • Initializes the platform and peripheral interfaces required by the SDI RX/TX and audio subsystems.

  • Initializes the SDI Audio Embed and Extract driver.

  • Registers interrupt handlers for:

    • SPDIF (AES3) RX

    • SPDIF (AES3) TX

    • SDI Audio Extract

    • SDI Audio Embed

After initialization, it presents a UART‑based main menu:

--------------------- --- MAIN MENU --- --------------------- i - Info => Shows information about the SDI RX stream, SDI TX stream. z - SDI TX & RX log => Shows log information for SDI TX & RX. d - Debug Info => Registers Dump. s - SDI Audio Pass-Through => Audio extracted from SDI RX is embedded back to SDI TX. a - AES3 Audio Capture and Playback => Audio extracted from SDI RX is played back on AES Output. => Audio captured from AES Input is embedded on to SDI TX.

The Info and related functions allow software to query SDI RX and TX stream parameters and SDI audio status.

6. Example application usage

The usage flow below assumes a typical Zynq UltraScale+ MPSoC platform with UHD‑SDI RX/TX subsystems instantiated as described in PG290.

6.1 Hardware setup

  • Board: e.g. ZCU106 or another board with UHD‑SDI RX/TX FMC or on‑board SDI connectors (match your design)

  • SDI connections:

    • Connect a valid SDI source (camera, pattern generator, or SDI output from another board) to the SDI RX input.

    • Connect the SDI TX output to an SDI monitor or analyzer.

  • Audio connections (optional):

    • For AES3/SPDIF capture and playback, connect the appropriate AES3 input and output ports as provided on your board or FMC.

Ensure that any SDI‑related clocks, transceivers, and reference clocks are configured as described in PG290 and the board documentation.

6.2 Vivado design

A typical hardware design includes:

  • SMPTE UHD‑SDI Receiver Subsystem (SDI RXSS) configured per PG290.

  • SMPTE UHD‑SDI Transmitter Subsystem (SDI TXSS) for pass‑through.

  • Audio extract and embed blocks, and SPDIF (AES3) interfaces, as required by the example.

  • Processor system (e.g. Zynq UltraScale+ MPSoC PS) with:

    • AXI4‑Lite connections to SDI RX, SDI TX, audio, and SPDIF IP

    • Interrupts from SDI RX/TX and audio blocks routed to the processor

Export the design as an XSA for software development.

6.3 Vitis / standalone application flow

  1. Create platform

    • In Vitis, create a standalone platform from the exported XSA that includes SDI RX/TX, audio, and SPDIF IP.

  2. Create application

    • Create a new application project on this platform.

    • Choose the SDI Pass Through Example if provided as a template, or import the example sources into a new standalone application.

  3. Build

    • Build the application to generate the ELF.

  4. Run on hardware

    • Program the PL with the bitstream.

    • Load and run the SDI pass‑through ELF on the processor.

6.4 Console interaction

  1. Open a UART console at the board’s default settings (for example 115200‑8‑N‑1).

  2. Power on or reset the board.

  3. Confirm the example banner and initialization messages, including:

    • SDI Pass Through Example banner

    • SDI AUDIO EMBED AND EXTRACT DRIVER ready

    • Successful registration of SPDIF and SDI audio interrupt handlers

  4. Use the main menu:

    • i – Show SDI RX and TX stream information

    • z – Show SDI RX/TX log information

    • d – Dump register debug information

    • s – Enable SDI audio pass‑through (embedded audio from SDI RX is re‑embedded into SDI TX)

    • a – Enable AES3 audio capture and playback (AES3 input to SDI TX, SDI RX audio to AES3 output)

7. Test log

7.1 SDI pass‑through example log

This section provides a reference log for the SDI pass‑through example.

Zynq MP First Stage Boot Loader Release 2024.1 Apr 4 2024 - 11:22:46 PMU-FW is not running, certain applications may not be supported. Set i2c mux... done ---------------------------------------- --- SDI Pass Through Example --- --- (c) 2018 by Xilinx, Inc. --- ---------------------------------------- Build Apr 15 2024 - 11:44:18 ---------------------------------------- SDI AUDIO EMBED AND EXTRACT DRIVER ready to use Successfully registered Spdif Rx interrupt handler Successfully registered Spdif Tx interrupt handler Successfully registered SDI Audio Extract interrupt handler Successfully registered SDI Audio Embed interrupt handler --------------------- --- MAIN MENU --- --------------------- i - Info => Shows information about the SDI RX stream, SDI TX stream. z - SDI TX & RX log => Shows log information for SDI TX & RX. d - Debug Info => Registers Dump. s - SDI Audio Pass-Through => Audio extracted from SDI RX is embedded back to SDI TX. a - AES3 Audio Capture and Playback => Audio extracted from SDI RX is played back on AES Output. => Audio captured from AES Input is embedded on to SDI TX. INFO>> SDI Rx: Input Locked ------------ SDI TX SubSystem ------------ SDI stream info ------------ Color Format: YUV_422 Color Depth: 10 Pixels Per Clock: 2 Mode: Progressive DSC Status: Uncompressed Frame Rate: 50Hz Resolution: 1920x1080@50Hz Pixel Clock: 148500 kHz SDI Mode: 3GA Bit Rate: Integer ST352 Payload: 0x180C989 INFO>> SDI Rx: Input Locked INFO>> SDI Rx: Lock Lost INFO>> SDI Rx: Input Locked ------------ SDI TX SubSystem ------------ SDI stream info ------------ Color Format: YUV_422 Color Depth: 10 Pixels Per Clock: 2 Mode: Progressive DSC Status: Uncompressed Frame Rate: 50Hz Resolution: 1920x1080@50Hz Pixel Clock: 148500 kHz SDI Mode: 3GA Bit Rate: Integer ST352 Payload: 0x180C989 ------------ SDI Audio info ------------ Audio Mode: SDI Audio Pass-Through SDI Audio Extract: Detected 3 Audio Groups G2: 48.0 KHz, 4 Active Channels, Sync Audio G3: 48.0 KHz, 4 Active Channels, Sync Audio G4: 48.0 KHz, 4 Active Channels, Sync Audio SDI Audio Embed: Embedding back all the incoming Audio Groups

8. Sequence Diagram:

The attached document provides a detailed description of the application and driver flow for SDI passthrough mode.

9. Change log

  • 2024.1

    • Initial documentation for SDI RXSS standalone driver pass‑through example.

    • Added:

      • Introduction and PG290 reference.

      • Driver features aligned with SMPTE UHD‑SDI RX subsystem capabilities.

      • Implementation overview and driver layering.

      • SDI pass‑through example description and usage steps.

      • Reference SDI pass‑through UART log.

Test cases

https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/v_sdirxss/examples