Ipipsu
- Shubhrajyoti Datta
- T, Harini
- Alvin Paul P
This page gives an overview of ipipsu driver.
Table of Contents
Introduction
This page gives an overview of ipipsu driver which is available as part of the Xilinx Vivado and SDK distribution.
The heterogeneous multiprocessor system uses the inter-processor interrupt (IPI) structure
to exchange short interrupt-driven messages between processors in the system. The IPI
architecture allows the passing of messages across the system without the complications of
autonomous read-write transactions and polling inefficiency.
Driver Sources
The source code for the driver is included with the Vitis Unified Software Platform installation, as well as being available in the Xilinx Github repository.
Driver Name | Path in Vitis | Path in Github |
|---|---|---|
| ipipsu | <Vitis Install Directory>/data/embedded/XilinxProcessorIPLib/drivers/ipipsu | https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/ipipsu |
Note: To view the sources for a particular release, use the rel-version tag in github. For example, for the 2020.1 release, the proper version of the code is: https://github.com/Xilinx/embeddedsw/tree/xilinx-v2020.1/XilinxProcessorIPLib/drivers/ipipsu
The driver source code is organized into different folders. The table below shows the ipipsu driver source organization.
| Directory | Description |
|---|---|
doc | Provides the API and data structure details |
data | Driver .tcl, .mdd and .yaml file |
examples | Example applications that show how to use the driver features |
| src | Driver source files, make and cmakelists file |
Note: AMD Xilinx embeddedsw build flow is changed from 2023.2 release to adapt to the new system device tree based flow. For further information, refer to the wiki page Porting embeddedsw components to system device tree (SDT) based flow - Xilinx Wiki - Confluence (atlassian.net).
The .yaml(in data folder) and CMakeLists.txt(in src folder) files are needed for the System Device Tree based flow. The Driver .tcl and .mdd files are for the older build flow which will be deprecated in the future.
Driver Implementation
For a full list of features supported by this IP, please refer Chapter 56: Inter-Processor Interrupts in Versal TRM (Versal platform) and Chapter 13: IPI Interrupts and Message Buffers in ZynqMP TRM
IPI Features
The IPIPSU block, provides the following features.- Supports processor communications including both an IPI interrupt structure and memory buffers to
exchange short private 32B messages between eight IPI agents. - Supports both blocking and nonblocking calls.
CRC :
We support CRC16 for IPI messages. The last word in IPI buffer is reserved for adding CRC for the IPI data. When ENABLE_IPI_CRC macro is defined,
IPI driver will calculate and add CRC to the last word while sending and will validate CRC while receiving IPI.
If CRC mismatch occurs, error response is returned.
Example Applications
Refer to the driver examples directory for various example applications that exercise the different features of the driver. Each application is linked in the table below. The following sections describe the usage and expected output of the various applications. These example applications can be imported into the Vitis IDE from the Board Support Package settings tab.
Links to Examples
Examples Path:
https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/ipipsu/examples
| Test Name | Example Source | Description |
|---|---|---|
| IPIPSU example | This example sends a message to itself and confirms the message. |
Example Application Usage
IPIPSU example
This example sends a message to itself and receives it.
Expected Output
Hello IPI! [Build: Jul 2 2021 07:11:56] Interrupt ID: 67 Message Content: W0: 0x5851F42D W1: 0x40B18CCF W2: 0x4BB5F646 W3: 0x47033129 W4: 0x30705B04 W5: 0x20FD5DB4 W6: 0x1A8B7F78 W7: 0x502959D8 Triggering IPI and Waiting for Response... ---->Enter Interrupt Handler Message Received: W0: 0x5851F42D W1: 0x40B18CCF W2: 0x4BB5F646 W3: 0x47033129 W4: 0x30705B04 W5: 0x20FD5DB4 W6: 0x1A8B7F78 W7: 0x502959D8 Sent back Inverted Message. <----Exit Interrupt Handler Received response. Message : Response W0 -> 0x5851F42D : 0xA7AE0BD2 W1 -> 0x40B18CCF : 0xBF4E7330 W2 -> 0x4BB5F646 : 0xB44A09B9 W3 -> 0x47033129 : 0xB8FCCED6 W4 -> 0x30705B04 : 0xCF8FA4FB W5 -> 0x20FD5DB4 : 0xDF02A24B W6 -> 0x1A8B7F78 : 0xE5748087 W7 -> 0x502959D8 : 0xAFD6A627 Successfully ran Ipipsu selftest Example
Changelog
2024.1
https://github.com/Xilinx/embeddedsw/blob/xlnx_rel_v2024.1/doc/ChangeLog#L461
2023.2
2023.1
https://github.com/Xilinx/embeddedsw/blob/xilinx_v2023.1/doc/ChangeLog#L98
2022.1
None
2021.2
2021.1
2020.2
2020.1
Related Links
- NA
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