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AXI UART 16550 standalone driver

AXI UART 16550 standalone driver

T

his page gives an overview of UART 16550 driver which is available as part of the Xilinx Vivado and SDK distribution.

Table of Contents

Introduction

The LogiCORE™ IP AXI Universal Asynchronous Receiver Transmitter (UART) 16550 connects to the Advanced
Microcontroller Bus Architecture (AMBA®) AXI and provides the controller interface for asynchronous serial
data transfer. This soft IP core is designed to connect through an AXI4-Lite interface.

Driver Sources

The source code for the driver is included with the Vitis Unified Software Platform installation, as well as being available in the Xilinx Github repository.

Driver Name

Path in Vitis

Path in Github

Driver Name

Path in Vitis

Path in Github

uartns550

<Vitis Install Directory>/data/embedded/XilinxProcessorIPLib/drivers/uartns550

https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/uartns550



Note: To view the sources for a particular release, use the rel-version tag in github.  For example, for the 2020.1 release, the proper version of the code is: https://github.com/Xilinx/embeddedsw/tree/xilinx-v2020.1/XilinxProcessorIPLib/drivers/uartns550

The driver source code is organized into different folders.  The table below shows the uartns550 driver source organization. 



Directory

Description

Directory

Description

doc

Provides the API and data structure details

data

Driver .tcl, .yaml and .mdd file

examples

Example applications that show how to use the driver features

src

Driver source files, make and cmakelists file

Note: AMD Xilinx embeddedsw build flow has been changed from 2023.2 release to adapt to the new system device tree based flow. For further information, refer to the wiki link Porting embeddedsw components to system device tree (SDT) based flow
The .yaml(in data folder) and CMakeLists.txt(in src folder) files are needed for the System Device Tree based flow. The Driver .tcl and .mdd files are for the older build flow which will be deprecated in future.

Driver Implementation

For a full list of features supported by this IP, please refer https://www.xilinx.com/support/documentation/ip_documentation/ds748_axi_uart16550.pdf

Features

  • AXI4-Lite interface for register access and data transfers

  • Hardware and software register compatible with all

  • standard 16450 and 16550 UARTs

  • Supports default core configuration for 9600 baud, 8 bits data length, 1 stop bit and no parity

  • Implements all standard serial interface protocols

    • 5, 6, 7 or 8 bits per character

    • Odd, Even or no parity detection and generation

    • 1, 1.5 or 2 stop bit detection and generation

    • Internal baud rate generator and separate receiver clock input

    • Modem control functions

    • Prioritized transmit, receive, line status and modem control interrupts

    • False start bit detection and recover

    • Line break detection and generation

    • Internal loopback diagnostic functionality

    • 16 character transmit and receive FIFOs

Known Issues and Limitations

None



Driver Supported Features

The UART 16550 Standalone driver support the below things.
All Controller Features supported.

Known issues and Limitations

  • None.

Example Applications

Refer to the driver examples directory for various example applications that exercise the different features of the driver. Each application is linked in the table below. The following sections describe the usage and expected output of the various applications.  These example applications can be imported into the Vitis IDE from the Board Support Package  settings tab. 



https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/uartns550/examples













Uartns550 interrupt example

xuartns550_intr_example.c

This example sends and receives data using interrupts

Uartns550 polled example

xuartns550_polled_example.c

This example sends and receives data using polling

Uartns550 hello world example

xuartns550_hello_world_example.c

This example transmits "Hello world" string

Uartns550 selftest_example

xuartns550_selftest_example.c

This example performs the basic selftest using the driver.

Uartns550 low_level_example

xuartns550_low_level_example.c

This example shows the usage of the low-level driver functions and macros of the driver.

Example Application Usage

Uartns550 interrupt example

This example sends and receives data using interrupts

Expected Output

Successfully ran Uartns550 interrupt Example

Uartns550 polled example

This example sends and receives data using polling

Expected Output



Successfully ran Uartns550 polled Example

Uartns550 hello world example

This example transmits "Hello world" string

Expected Output



Successfully ran Uartns550 hello world Example

Example Design Architecture

NA

Change Log

2025.2

embeddedsw/doc/ChangeLog at xlnx_rel_v2025.2 · Xilinx/embeddedsw · GitHub

2025.1

https://github.com/Xilinx/embeddedsw/blob/xlnx_rel_v2025.1/doc/ChangeLog#L184

2024.2

https://github.com/Xilinx/embeddedsw/blob/xlnx_rel_v2024.2/doc/ChangeLog#L257

2024.1

https://github.com/Xilinx/embeddedsw/blob/xlnx_rel_v2024.1/doc/ChangeLog#L937

2023.2

https://github.com/Xilinx/embeddedsw/blob/xlnx_rel_v2023.2/doc/ChangeLog#L134

2023.1

None

2022.2

None

2022.1

None

2021.2

None

2021.1

https://github.com/Xilinx/embeddedsw/blob/xilinx_v2021.1/doc/ChangeLog#L64

2020.2

https://github.com/Xilinx/embeddedsw/blob/xilinx-v2020.2/doc/ChangeLog#L708

2020.1



https://github.com/Xilinx/embeddedsw/blob/xilinx-v2020.1/doc/ChangeLog#L129

2019.2

None

2019.1

None

2018.3

None

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