This page gives an overview of UART 16550 driver which is available as part of the Xilinx Vivado and SDK distribution.
The LogiCORE™ IP AXI Universal Asynchronous Receiver Transmitter (UART) 16550 connects to the Advanced
Microcontroller Bus Architecture (AMBA®) AXI and provides the controller interface for asynchronous serial
data transfer. This soft IP core is designed to connect through an AXI4-Lite interface.
The source code for the driver is included with the Vitis Unified Software Platform installation, as well as being available in the Xilinx Github repository.
The driver source code is organized into different folders. The table below shows the uartns550 driver source organization.
- AXI4-Lite interface for register access and data transfers
- Hardware and software register compatible with all
- standard 16450 and 16550 UARTs
- Supports default core configuration for 9600 baud, 8 bits data length, 1 stop bit and no parity
- Implements all standard serial interface protocols
- 5, 6, 7 or 8 bits per character
- Odd, Even or no parity detection and generation
- 1, 1.5 or 2 stop bit detection and generation
- Internal baud rate generator and separate receiver clock input
- Modem control functions
- Prioritized transmit, receive, line status and modem control interrupts
- False start bit detection and recover
- Line break detection and generation
- Internal loopback diagnostic functionality
- 16 character transmit and receive FIFOs
Known Issues and Limitations
Driver Supported FeaturesThe UART 16550 Standalone driver support the below things.All Controller Features supported.
Known issues and Limitations
Refer to the driver examples directory for various example applications that exercise the different features of the driver. Each application is linked in the table below. The following sections describe the usage and expected output of the various applications. These example applications can be imported into the Vitis IDE from the Board Support Package settings tab. https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/uartns550/examples
Example Application Usage
Uartns550 interrupt example
This example sends and receives data using interrupts
Successfully ran Uartns550 interrupt Example
Uartns550 polled example
This example sends and receives data using polling
Successfully ran Uartns550 polled Example
Uartns550 hello world example
This example transmits "Hello world" string
Successfully ran Uartns550 hello world Example
Example Design Architecture