This page gives an overview of clk_wiz BareMetal driver.

Table of Contents

Introduction

This page gives an overview of clk_wiz driver which is available as part of the Xilinx Vivado and SDK distribution.

For more information, please refer   TRM which includes links to the official documentation and resource utilization. 

Driver Sources

The source code for the driver is included with the Vitis Unified Software Platform installation, as well as being available in the Xilinx Github repository. 

The driver source code is organized into different folders.  The table below shows the clk_wiz driver source organization. 

Note: AMD Xilinx embeddedsw build flow has been changed from 2023.2 release to adapt to the new system device tree based flow. For further information, refer to the wiki link Porting embeddedsw components to system device tree (SDT) based flow

The .yaml(in data folder) and CMakeLists.txt(in src folder) files are needed for the System Device Tree based flow. The Driver .tcl and .mdd files are for the older build flow which will be deprecated in future.

Driver Implementation

For a full list of features supported by this IP, please refer  TRM

Features

1. Accepts up to two input clocks and up to
   seven output clocks per clock network.
2.  Provides an AXI4-Lite interface for
   dynamically reconfiguring the clocking
   primitives for Multiply, Divide, Phase Shift/
   Offset, or Duty Cycle.

Known Issues and Limitations

• None

Example Applications

Refer to the driver examples directory for various example applications that exercise the different features of the driver. Each application is linked in the table below. The following sections describe the usage and expected output of the various applications.  These example applications can be imported into the Vitis IDE from the Board Support Package  settings tab. 

Links to Examples

Examples Path:
https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/clk_wiz/examples

Example Application Usage

Clock Wizard versal example

This examples does basic rate setting  of clocking wizard.

Expected Output 

------------------------------------------
CLK_WIZARD example
------------------------------------------
Successfully ran CLK_WIZARD example

Clock Wizard Interrupt mode example

 This example tests the clock monitoring example

Expected Output

------------------------------------------
CLK_WIZARD example
------------------------------------------
Successfully ran CLK_WIZ Monitor interrupt example

Example Design Architecture

NA

Performance

NA

Change Log

2024.2

https://github.com/Xilinx/embeddedsw/blob/xilinx_v2024.2/doc/ChangeLog#L55

2024.1

https://github.com/Xilinx/embeddedsw/blob/xilinx_v2024.1/doc/ChangeLog#L201

2023.2

embeddedsw/doc/ChangeLog at xilinx_v2023.2 · Xilinx/embeddedsw · GitHub

2023.1

None

2022.2

https://github.com/Xilinx/embeddedsw/blob/xilinx_v2022.2/doc/ChangeLog#L90

2022.1

None

2021.1

None

2020.2

https://github.com/Xilinx/embeddedsw/blob/xilinx_v2021.1/doc/ChangeLog#L1170

2020.1

https://github.com/Xilinx/embeddedsw/blob/xilinx_v2021.1/doc/ChangeLog#L2100

Related Links

• http://www.wiki.xilinx.com/Baremetal+Drivers+and+Libraries