Clocking Wizard Standalone driver


This page gives an overview of clk_wiz driver which is available as part of the Xilinx Vivado and SDK distribution.

For more information, please refer   TRM which includes links to the official documentation and resource utilization. 

Driver Sources

The source code for the driver is included with the Vitis Unified Software Platform installation, as well as being available in the Xilinx Github repository. 

Driver Name

Path in Vitis

Path in Github


<Vitis Install Directory>/data/embedded/XilinxProcessorIPLib/drivers/clk_wiz

Note: To view the sources for a particular release, use the rel-version tag in github.  For example, for the 2020.1 release, the proper version of the code is:

The driver source code is organized into different folders.  The table below shows the clk_wiz driver source organization. 



Provides the API and data structure details


Driver .tcl and .mdd file


Example applications that show how to use the driver features


Driver source files

Driver Implementation

For a full list of features supported by this IP, please refer  TRM


  1. Accepts up to two input clocks and up to
    seven output clocks per clock network.
  2.  Provides an AXI4-Lite interface for
    dynamically reconfiguring the clocking
    primitives for Multiply, Divide, Phase Shift/
    Offset, or Duty Cycle.

Known Issues and Limitations

  • None

Example Applications

Refer to the driver examples directory for various example applications that exercise the different features of the driver. Each application is linked in the table below. The following sections describe the usage and expected output of the various applications.  These example applications can be imported into the Vitis IDE from the Board Support Package  settings tab. 

Links to Examples

Examples Path:

Test Name

Example Source

Clocking wizard versal example


Example to set the output frequency to a specific rate for versal platform.
Clocking wizard  Interrupt mode example


 This example tests the clock monitoring example

Example Application Usage

Clock Wizard versal example

This examples does basic rate setting  of clocking wizard.

Expected Output 

CLK_WIZARD example
Successfully ran CLK_WIZARD example

Clock Wizard Interrupt mode example

 This example tests the clock monitoring example

Expected Output

CLK_WIZARD example
Successfully ran CLK_WIZ Monitor interrupt example

Example Design Architecture




Change Log





Related Links