This page gives an overview of the bare-metal driver support for the Octal SPI controller.

1 Introduction
2 Driver Sources
3 Driver Implementation
- 3.1 Features
- 3.2 Known Issues and Limitations
- 3.3 Supported Flash vendors
4 Example Applications
- 4.1 Links to Examples
- 4.2 Example Application Usage
  - 4.2.1 OSPI Polled mode example
  - 4.2.2 OSPI Interrupt mode example
  - 4.2.3 OSPI Non-blocking Polled mode example
5 Example Design Architecture
6 Performance
7 Change Log
- 7.1 2024.2
- 7.2 2024.1
- 7.3 2023.2
- 7.4 2023.1
- 7.5 2022.2
- 7.6 2022.1
- 7.7 2021.2
- 7.8 2021.1
- 7.9 2020.2
- 7.10 2020.1
- 7.11 2019.2
- 7.12 2019.1
8 Related Links

Introduction

The octal SPI (OSPI) controller can access one or two flash devices using several different methods. The controller is located with the other flash memory controllers in the PMC. The I/O
interface is routed to the PMC MIO pin bank 0. OSPI is commonly used as a boot device. The controller provides multiple ways to read and write the flash memory:
• STIG/PIO read/write (software triggered instruction generator)
• Direct read/write with address remap
• Non-DMA indirect read/write via AXI slave interface
• DMA indirect read using AXI master interface

For more information, please refer Chapter 73: Octal SPI Controller in Versal TRM which includes links to the official documentation and resource utilization.

Driver Sources

The source code for the driver is included with the Vitis Unified Software Platform installation, as well as being available in the Xilinx Github repository.

Driver Name	Path in Vitis	Path in Github

Driver Name	Path in Vitis	Path in Github
ospipsv	<Vitis Install Directory>/data/embedded/XilinxProcessorIPLib/drivers/ospipsv	https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/ospipsv

Note: To view the sources for a particular release, use the rel-version tag in github. For example, for the 2020.1 release, the proper version of the code is: https://github.com/Xilinx/embeddedsw/tree/xilinx-v2020.1/XilinxProcessorIPLib/drivers/ospipsv

The driver source code is organized into different folders. The table below shows the ospipsv driver source organization.

Directory	Description

Directory	Description
doc	Provides the API and data structure details
data	Driver .tcl , .mdd and .yaml files
examples	Example applications that show how to use the driver features
src	Driver source files, make and cmakelists file

Note: AMD Xilinx embeddedsw build flow is changed from 2023.2 release to adapt to the new system device tree based flow. For further information, refer to the wiki page Porting embeddedsw components to system device tree (SDT) based flow - Xilinx Wiki - Confluence (atlassian.net).

The .yaml(in data folder) and CMakeLists.txt(in src folder) files are needed for the System Device Tree based flow. The Driver .tcl and .mdd files are for the older build flow which will be deprecated in the future.

Driver Implementation

For a full list of features supported by this IP, please refer Chapter 73: Octal SPI Controller in Versal TRM

Features

Software triggered IO mode (STIG) up to 8-bytes of data transfers.
Indirect DMA reads.
Local SRAM to reduce AHB overhead.
Supports SDR and DDR protocols.
Programmable master mode clock frequencies.
Programmable peripheral selects (chip select).
Support for Single and Octal instructions.
Interrupts and polled based operations.

Known Issues and Limitations

Macronix flash works only up to 150MHz.

Supported Flash vendors

Micron
ISSI
Gigadevice
Macronix

Example Applications

Refer to the driver examples directory for various example applications that exercise the different features of the driver. Each application is linked in the table below. The following sections describe the usage and expected output of the various applications. These example applications can be imported into the Vitis IDE from the Board Support Package settings tab.

Links to Examples

Examples Path:
https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/ospipsv/examples

Test Name	Example Source	Description

Test Name

Example Source

Description

OSPI Polled mode example

xospipsv_flash_polled_example.c

xospipsv_flash_config.h

This examples does basic read and write test from the flash device in Polled mode.

OSPI Interrupt mode example

xospipsv_flash_intr_example.c

xospipsv_flash_config.h

This examples does basic read and write test from the flash device in Interrupt mode.

OSPI Non-blocking Polled mode example

xospipsv_flash_non_blocking_read_example.c

xospipsv_flash_config.h

This examples does basic read and write test from the flash device in Non-blocking Polled mode.

Example Application Usage

OSPI Polled mode example

This examples does basic read and write test from the flash device in Polled mode.

Expected Output

OSPI Interrupt mode example

OSPIPSV Flash Polled Example Test
FlashID = 0x2C 0x5B 0x1A 0x10 0x41 0x0 0x96 0x78 0x0
EraseCmd 0xDC
WriteCmd: 0x12
ReadCmd 0xCC
Successfully ran OSPIPSV Flash Polled Ex

This examples does basic read and write test from the flash device in Interrupt mode.

Expected Output

OSPIPSV Flash Interrupt Example Test
Execuing on the a72
FlashID = 0x2C 0x5B 0x1A 0x10 0x41 0x0 0x96 0x78 0x0
EraseCmd 0xDC
WriteCmd: 0x12
ReadCmd 0xCC
Successfully ran OSPIPSV Flash Interrupt Example

OSPI Non-blocking Polled mode example

This examples does basic read and write test from the flash device in Non-blocking Polled mode.

Expected Output

OSPIPSV Flash Polled non-blocking read Example Test
FlashID = 0x2C 0x5B 0x1A 0x10 0x41 0x0 0x96 0x78 0x0
EraseCmd 0xDC
WriteCmd: 0x12
ReadCmd 0xCC
Successfully ran OSPIPSV Flash non-blocking read Ex