Mutex standalone
This page gives an overview of mutex bare-metal driver support which is available as part of the Xilinx Vivado.
Table of Contents
Introduction
This page gives an overview of mutex driver which is available as part of the Xilinx Vivado and SDK distribution.
In a multi-processor environment, the processors share common resources. The Mutex core provides a mechanism for mutual exclusion to enable one process to gain exclusive access to a particular resource.
The Mutex core contains a configurable number of mutexes.
Each of these can be associated with a 32-bit user configuration register to store arbitrary data.
Driver Sources
The source code for the driver is included with the Vitis Unified Software Platform installation, as well as being available in the Xilinx Github repository.
Driver Name | Path in Vitis | Path in Github |
|---|---|---|
mutex | <Vitis Install Directory>/data/embedded/XilinxProcessorIPLib/drivers/mutex | https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/mutex |
The driver source code is organized into different folders. The table below shows the mutex driver source organization.
Directory | Description |
|---|---|
doc | Provides the API and data structure details |
data | Driver .tcl , .mdd and .yaml files |
examples | Example applications that show how to use the driver features |
src | Driver source files, make and cmakelists file |
Note: AMD Xilinx embeddedsw build flow is changed from 2023.2 release to adapt to the new system device tree based flow. For further information, refer to the wiki page Porting embeddedsw components to system device tree (SDT) based flow - Xilinx Wiki - Confluence (atlassian.net).
The .yaml(in data folder) and CMakeLists.txt(in src folder) files are needed for the System Device Tree based flow. The Driver .tcl and .mdd files are for the older build flow which will be deprecated in the future.
Driver Implementation
For a full list of features supported by this IP, please refer Mutex Product Guide
Features
Configurable number of AXI4-Lite interfaces from 0 to 8
Configurable asynchronous or synchronous interface operation
Configurable USER register
Configurable number of mutexes
Configurable CPUID width
Configurable enhanced security through hardware identification support
Known Issues and Limitations
SDTGen assumes that mutex is always connected between PL processors. The DTS generation fails if any PS/PL processor is not connected to the mutex within the design.
Example Applications
Refer to the driver examples directory for various example applications that exercise the different features of the driver. Each application is linked in the table below. The following sections describe the usage and expected output of the various applications. These example applications can be imported into the Vitis IDE from the Board Support Package settings tab.
Links to Examples
Examples Path:
https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/mutex/examples
Test Name | Example Source | Description |
|---|---|---|
Mutex example | This example attempts to lock the Mutex from the processor identified as 0 to prevent the other processor from getting the lock. |
Example Application Usage
Mutex example
Mutex is used in from one processor to prevent locking from the other processor can be tested by selecting xmutex_tapp_example.c
Refer to https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/mutex/examples/readme.txtor more information.
Mutex example
Expected Output
Xilinx Zynq MP First Stage Boot Loader
Release 2021.1 May 4 2021 - 08:06:56
PMU-FW is not running, certain applications may not be supported.
PMU Firmware 2021.1 May 4 2021 08:06:56
PMU_ROM Version: xpbr-v8.1.0-0
MutexExample : Starts.
MutexExample : Successfully ran Mutex tapp Example
MutexExample : Ends.Change log
2025.2
None
2025.1
2024.2
2024.1
2023.2
None
2023.1
None
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