Mutex standalone

Introduction

This page gives an overview of mutex driver which is available as part of the Xilinx Vivado and SDK distribution.

In a multi-processor environment, the processors share common resources. The Mutex core provides a mechanism for mutual exclusion to enable one process to gain exclusive access to a particular resource.
The Mutex core contains a configurable number of mutexes.
Each of these can be associated with a 32-bit user configuration register to store arbitrary data.

Driver Sources

The source code for the driver is included with the Vitis Unified Software Platform installation, as well as being available in the Xilinx Github repository. 

Driver Name

Path in Vitis

Path in Github

mutex

<Vitis Install Directory>/data/embedded/XilinxProcessorIPLib/drivers/mutex

https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/mutex

The driver source code is organized into different folders.  The table below shows the ipipsu driver source organization. 

Directory
Description

doc

Provides the API and data structure details

data

Driver .tcl and .mdd file

examples

Example applications that show how to use the driver features

src

Driver source files



Driver Implementation

For a full list of features supported by this IP, please refer Chapter 73: Octal SPI Controller in Versal TRM

Features

  1.  Configurable number of AXI4-Lite interfaces from 0 to 8
  2. Configurable asynchronous or synchronous interface operation
  3.  Configurable USER register
  4.  Configurable number of mutexes
  5.  Configurable CPUID width
  6.  Configurable enhanced security through hardware identification support

Known Issues and Limitations

  • None


Example Applications

Refer to the driver examples directory for various example applications that exercise the different features of the driver. Each application is linked in the table below. The following sections describe the usage and expected output of the various applications.  These example applications can be imported into the Vitis IDE from the Board Support Package  settings tab. 

Links to Examples

Examples Path:
https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/mutex/examples

Test Name

Example Source

Description
Mutex example

xmutex_tapp_example.c


This example attempts to lock the Mutex from the processor identified as 0

 to prevent the other processor from getting the lock.

Example Application Usage


Test cases
Mutex example
Mutex is used in from one processor to prevent locking from the other processor can be tested by selecting xmutex_tapp_example.c
Refer to https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/mutex/examples/readme.txtor more information.


Mutex example

Expected Output

Xilinx Zynq MP First Stage Boot Loader
Release 2021.1 May 4 2021 - 08:06:56
PMU-FW is not running, certain applications may not be supported.
PMU Firmware 2021.1 May 4 2021 08:06:56
PMU_ROM Version: xpbr-v8.1.0-0
MutexExample : Starts.
MutexExample : Successfully ran Mutex tapp Example
MutexExample : Ends.

Change log

2021.2

2021.1

  • None

2020.2

  • None

2020.1

  • None

2019.2

  • None

2019.1