AXI4-Stream FIFO Standalone Driver

LLFIFO Standalone Driver


Table of Contents

Introduction

This page gives an overview of the llfifo driver which is available as part of the Xilinx Vivado and SDK distribution.

The LogiCORE™ IP AXI4-Stream FIFO core allows memory mapped access to an AXI4-Stream interface.
The core can be used to interface to AXI Streaming IPs, Similar to the LogiCORE IP AXI Ethernet core,
Without having to use a full DMA solution. The principal operation of this core allows the write or read
Of data packets to or from a device without any concern over the AXI4-Stream interface signaling.
You can easily manage the AXI4-Stream interfaces as they are transparent.

Driver Sources

The source code for the driver is included with the Vitis Unified Software Platform installation, as well as being available in the Xilinx Github repository. 

Driver Name

Path in Vitis

Path in Github

llfifo

<Vitis Install Directory>/data/embedded/XilinxProcessorIPLib/drivers/llfifo

https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/llfifo

Note: To view the sources for a particular release, use the rel-version tag in github.  For example, for the 2020.1 release, the proper version of the code is: https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/llfifo


The driver source code is organized into different folders.  The table below shows the llfifo driver source organization. 

DirectoryDescription

doc

Provides the API and data structure details

data

Driver .tcl and .mdd file

examples

Example applications that show how to use the driver features

src

Driver source files

Driver Implementation

For a full list of features supported by this IP, please refer TRM

Features

  1. Supports Configurable data interface types (AXI4 or AXI4-lite).
  2. Supports Configurable data widths
  3. Supports Configurable FIFO depth feature
  4. Supports TX and RX cut-through mode feature
  5. Supports Independent configuration of the Tx and Rx data FIFO's.
  6. Supports Full duplex operation.

Known Issues and Limitations

  • None

Example Applications

Refer to the driver examples directory for various example applications that exercise the different features of the driver. Each application is linked in the table below. The following sections describe the usage and expected output of the various applications.  These example applications can be imported into the Vitis IDE from the Board Support Package  settings tab. 

Links to Examples

Examples Path:
https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/llfifo/examples

Test Name

Example Source

Description
llfifo Polled mode example

xllfifo_polling_example.c


This example is the polling example for the FIFO it assumes that at the h/w level FIFO is connected in
Loopback. In these we write a known amount of data to the FIFO and Receive the data and compare with the data transmitted.
llfifo Interrupt mode example

xllfifo_interrupt_example.c


This example is the interrupt example for the FIFO it assumes that at the
H/w level FIFO is connected in loopback. In these, we write a known amount of data to the FIFO and wait for interrupts and after
Completely receiving the data compares it with the data transmitted.

Example Application Usage

llfifo Polled mode example

This example is the polling example for the FIFO it assumes that at the h/w level FIFO is connected in
Loopback. In these we write a known amount of data to the FIFO and Receive the data and compare with the data transmitted.

Expected Output