AXI Ethernet Standalone Driver

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Last updated: Sept 23, 2024 by harinik
4 min read
This page gives an overview of the bare-metal driver support for the Xilinx® AXI 1G/2.5G Ethernet Subsystem soft IP.   


Table of Contents

Introduction


The AXI 1G/2.5G Ethernet Subsystem core is a soft Xilinx IP core for use with the Xilinx Vivado® Design Suite. The Xilinx® AXI Ethernet Subsystem implements a tri-mode (10/100/1000 Mb/s) Ethernet MAC or a 10/100 Mb/s Ethernet MAC. This core supports the use of MII, GMII, SGMII, RGMII, and 1000BASE-X interfaces to connect a media access control (MAC) to a Physical-side interface (PHY) chip. It also provides an on-chip PHY for 1G/2.5G SGMII and 1000/2500 BASE-X modes. The MDIO interface is used to access PHY Management registers. This subsystem optionally enables TCP/UDP full checksum Offload, VLAN stripping, tagging, translation and extended filtering for multicast frames features.

For more information, please refer to the AXI Ethernet product page which includes links to the official documentation and resource utilization. 

Driver Sources

The source code for the driver is included with the Vitis Unified Software Platform installation, as well as being available in the Xilinx Github repository. 


Driver NamePath in VitisPath in Github
axiethernet<Vitis Install Directory>/data/embedded/XilinxProcessorIPLib/drivers/axiethernet_<version>https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/axiethernet


Note: To view the sources for a particular release, use the rel-version tag in github.  For example, for the 2020.1 release, the proper version of the code is: https://github.com/Xilinx/embeddedsw/tree/xilinx-v2020.1/XilinxProcessorIPLib/drivers/axiethernet


The driver source code is organized into different folders.  The table below shows the axiethernet driver source organization. 

DirectoryDescription
doc

Provides the API and data structure details

dataDriver .tcl, .mdd file and .yaml files
examplesExample applications that show how to use the driver features
srcDriver source files, make and cmake files

Note: AMD Xilinx embeddedsw build flow is changed from 2023.2 release to adapt to the new system device tree based flow. For further information, refer to the wiki page Porting embeddedsw components to system device tree (SDT) based flow - Xilinx Wiki - Confluence (atlassian.net).

The .yaml(in data folder) and CMakeLists.txt(in src folder) files are needed for the System Device Tree based flow. The Driver .tcl and .mdd files are for the older build flow which will be deprecated in the future.

Driver Implementation

For a full list of features supported by this IP, please refer to the AXI Ethernet product page.  


Features

The AXI Ethernet Standalone driver supports the following features: 
  • Supports all 1G phy-interface types MII, GMII, RGMII, SGMII and 1000base-x
  • Supports VLAN Frames
  • Supports Pause frames and flow control features
  • Support for AXI DMA Ethernet-based designs
  • Support for Axi Ethernet FIFO based designs
  • Support for Axi MCDMA Ethernet-based designs
  • Supports different Speeds 10/100/1000 Mbps
  • Supports Partial/Full Checksum offloading
  • Supports 2.5G buffered mode feature.

Known Issues and Limitations

The following is a list of known limitations of the driver and features of the IP that are not currently implemented: 

  • IEEE 1588 feature is not supported
  • No Support when 2.5G Ethernet is configured for Non-Buffered/Processor mode
  • No Support when 1G Ethernet is configured in Non-Buffered/Processor Mode
  • AXI Ethernet + FIFO examples are not ported to SDT flow

Example Design Architecture 

The examples assumes that AXI Ethernet AXI4-Stream bus is connected to AXIDMA/MCMDA/FIFO IP. 



Example Applications

Refer to the driver examples directory for various example applications that exercise the different features of the driver. Each application is linked in the table below. The following sections describe the usage and expected output of the various applications.  These example applications can be imported into the Vitis IDE from the Board Support Package  settings tab. 

Links to Examples

Examples Path: https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/axiethernet/examples

Test NameExample SourceDescription
Frame transfer with FIFO interruptxaxiethernet_example_intr_fifo.cThis example utilize the Axi Ethernet interrupt driven FIFO packet transfer mode to send and receive frames.
Frame transfer with FIFO pollingxaxiethernet_example_polled.cThis example utilize the Axi Ethernet polling driven FIFO packet transfer mode to send and receive frames.
Frame transfer with MCMDA interruptxaxiethernet_example_intr_mcdma.cThis example utilize the Axi Ethernet interrupt driven MCDMA packet transfer mode to send and receive frames.
Frame transfer with MCMDA pollingxaxiethernet_example_mcdma_poll.cThis example utilize the Axi Ethernet polling driven MCDMA packet transfer mode to send and receive frames.
Frame transfer with AXIDMA SG interruptxaxiethernet_example_intr_sgdma.cThis example utilize the Axi Ethernet interrupt driven SGDMA mode to send and receive frames.
Ping request with MCDMA pollingxaxiethernet_mcdma_ping_req_example.cThis example utilize the Axi Ethernet polling driven MCDMA packet transfer mode to send ping request frames.
Extended multicast with AXI DMA SG interruptxaxiethernet_example_extmulticast.cThis example utilize the Axi Ethernet interrupt driven SGDMA packet transfer mode to send and receive frames.
It demonstrates the extended multicast capability
Extended VLAN with AXI DMA SG interruptxaxiethernet_example_extvlan.cThis example utilize the Axi Ethernet interrupt driven SGDMA packet transfer mode to send and receive frames.
It demonstrates the extended VLAN capability

Example Application Usage

Frame transfer with FIFO interrupt

This example utilize the Axi Ethernet interrupt driven FIFO packet transfer mode to send and receive frames.

Expected Output

--- Enter main() ---
This test may take several minutes to finish
Successfully ran Axiethernet intr fifo Example
--- Exiting main() ---

Frame transfer with FIFO polling

This example utilize the Axi Ethernet polling driven FIFO packet transfer mode to send and receive frames.

Expected Output

--- Enter main() ---
This test may take several minutes to finish
Successfully ran Axiethernet poll mode fifo Example
--- Exiting main() ---

Frame transfer with MCMDA interrupt

This example utilize the Axi Ethernet interrupt driven MCDMA packet transfer mode to send and receive frames.

Expected Output

--- Enter main() ---
This test may take several minutes to finish
Test passed
--- Exiting main() ---

Frame transfer with MCMDA polling

This example utilize the Axi Ethernet polling driven MCDMA packet transfer mode to send and receive frames.

Expected Output

--- Enter main() ---
This test may take several minutes to finish
Polled Mode Test passed
--- Exiting main() ---

Frame transfer with AXIDMA SG interrupt

This example utilize the Axi Ethernet interrupt driven SGDMA mode to send and receive frames.

Expected Output

--- Enter main() ---
This test may take several minutes to finish
Successfully ran Axiethernet intr sgdma Example
--- Exiting main() ---

Ping request with MCDMA polling

This example utilize the Axi Ethernet polling driven MCDMA packet transfer mode to send ping request frames.

Expected Output

DMA init success
Cfg init success
BD seutp done
Successfully ran Axi Ethernet ping request Example

Extended multicast with AXI DMA SG interrupt

This example utilize the Axi Ethernet interrupt driven SGDMA packet transfer mode to send and receive frames. It demonstrates the extended multicast capability

Expected Output

--- Enter main() ---
This test may take several minutes to finish
Successfully ran Axiethernet extmulticast Example
--- Exiting main() ---

Extended VLAN with AXI DMA SG interrupt

This example utilize the Axi Ethernet interrupt driven SGDMA packet transfer mode to send and receive frames. It demonstrates the extended VLAN capability

Expected Output

--- Enter main() ---
This test may take several minutes to finish
Successfully ran Axiethernet extvlan Example
--- Exiting main() ---


Change Log

2024.1

https://github.com/Xilinx/embeddedsw/blob/xilinx_v2024.1/doc/ChangeLog#L110

2023.2

 https://github.com/Xilinx/embeddedsw/blob/xilinx_v2023.2/doc/ChangeLog#L528

2023.1

https://github.com/Xilinx/embeddedsw/blob/xilinx_v2023.1/doc/ChangeLog#L455

2022.2

None

2022.1

https://github.com/Xilinx/embeddedsw/blob/xilinx_v2022.1/doc/ChangeLog#L15

2021.2

https://github.com/Xilinx/embeddedsw/blob/xlnx_rel_v2021.2/doc/ChangeLog#L72

2021.1

https://github.com/Xilinx/embeddedsw/blob/xlnx_rel_v2021.1/doc/ChangeLog#L403


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