The AXI 1G/2.5G Ethernet Subsystem core is a soft Xilinx IP core for use with the Xilinx Vivado® Design Suite. The Xilinx® AXI Ethernet Subsystem implements a tri-mode (10/100/1000 Mb/s) Ethernet MAC or a 10/100 Mb/s Ethernet MAC. This core supports the use of MII, GMII, SGMII, RGMII, and 1000BASE-X interfaces to connect a media access control (MAC) to a Physical-side interface (PHY) chip. It also provides an on-chip PHY for 1G/2.5G SGMII and 1000/2500 BASE-X modes. The MDIO interface is used to access PHY Management registers. This subsystem optionally enables TCP/UDP full checksum Offload, VLAN stripping, tagging, translation and extended filtering for multicast frames features.

For more information, please refer to the AXI Ethernet product page which includes links to the official documentation and resource utilization.