AXI Ethernet Standalone Driver
Table of Contents
This page gives an overview of axi ethernet driver which is available as part of the Xilinx Vivado and SDK distribution.
The Xilinx® AXI Ethernet Subsystem implements a tri-mode (10/100/1000 Mb/s) Ethernet MAC or a 10/100 Mb/s Ethernet MAC. This core supports the use of MII, GMII, SGMII, RGMII, and 1000BASE-X interfaces to connect a media access control (MAC) to a Physical-side interface (PHY) chip. It also provides an on-chip PHY for 1G/2.5G SGMII and 1000/2500 BASE-X modes. The MDIO interface is used to access PHY Management registers. This subsystem optionally enables TCP/UDP full checksum Offload, VLAN stripping, tagging, translation and extended filtering for multicast frames features.
How to enableSource Path for the driverhttps://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/axiethernetDriver source code is organized into different folders. Below diagram shows the axiethernet driver source organization
axiethernet|- doc - Provides the API and data structure details
- data - Driver tcl and MDD file.|- examples - Reference application to show how to use the driver APIs and calling sequence|- src- Driver source files
- Support for MII, GMII, RGMII, SGMII, and 1000BASE-X PHY interfaces
- Support for 1000BASE-X and SGMII over Select Input/Output (I/O) Low Voltage Differential Signaling (LVDS)
- Support for pause frames for flow control
- Media Independent Interface Management (also called as MII), is used for accessing the PHY registers
- Ethernet Audio Video Bridging (AVB) support
- AXI4-Stream transmit/receive interface
- Support for 2.5G Ethernet. This feature is enabled for the following devices: Kintex®-7, Virtex®-7 with GTH and GTX transceivers Artix®-7 devices with GTP and speed grade -2 and -3 UltraScale™, UltraScale+™ devices with GTH and GTY transceivers
- IEEE Standard 1588 Support
- AXI4-Lite register interface
Standalone Driver Supported FeaturesThe AXI Ethernet Standalone driver supports the below things.
- Supports all 1G phy-interface types MII, GMII, RGMII, SGMII and 1000base-x
- Supports VLAN Frames
- Supports Pause frames and flow control features
- Support for AXI DMA Ethernet-based designs
- Support for Axi Ethernet FIFO based designs
- Support for Axi MCDMA Ethernet-based designs
- Supports different Speeds 10/100/1000 Mbps
- Supports Partial/Full Checksum offloading
- Supports 2.5G buffered mode feature.
Features not supported
- IEEE 1588 feature is not supported
- No Support when 2.5G Ethernet is configured for Non-Buffered/Processor mode
- No Support when 1G Ethernet is configured in Non-Buffered/Processor Mode
Interop- PHY device Marvell 88E1116 has been tested on KC705 evaluation board- PHY device TI DP83867 SGMII have been tested on VCU118 board.
Test casesAxi Ethernet DMA ExampleAxi Ethernet basic AXI DMA loopback example can be tested by selecting xaxiethernet_example_intr_sgdma.c, xaxiethernet_example_util.c and xaxiethernet_example.h from the driver.Refer to https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/axiethernet/examples/readme.txt for more information.Axi Ethernet FIFO ExampleAxi Ethernet basic AXI FIFO loopback example can be tested by selecting xaxiethernet_example_intr_fifo.c, xaxiethernet_example_util.c and xaxiethernet_example.h from the driver.Refer to https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/axiethernet/examples/readme.txt for more information.Known Issues/Limitations
- At the h/w level if the MAC reference clock is driving from onboard clock oscillator e.g si570 or si5324. Make sure clock is programmed to the proper clock value before performing any operations on the MAC.
- Support parallel make execution.
- Add versal support.
- Fix bsp generation error in a custom design.
257c0d9e3742 BSP: Consolidate and add the drivers xdebug.h data to common xdebug.h
4dc85994d6fb Makefile: Remove realpath command
ad4739446424 axiethernet: Modify makefile to support parallel make execution
14a8bb9f1bc8 axiethernet: Add support for versal silicon
300a9c894a55 axiethernet: Fix bsp generation error in a custom design
- Clean up old versions for axiethernet driver
- In debug mode fix return value of XAxiEthernet_ReadReg
- In driver tcl use "::hsi::utils::get_connected_intf" API
- Trivial code cleanup i.e Removed the assert condition for speed
500b39a axiethernet: Clean up old versions for axiethernet driver
5191a3a axiethernet: In debug mode fix return value of XAxiEthernet_ReadReg
14eefd8 axiethernet: In driver tcl use "::hsi::utils::get_connected_intf" API
acf82d5 axiethernet: Removed the assert condition for speed.
- In driver tcl use an identifiable suffix for global variables
db36090 axiethernet: Use an identifiable suffix for global variables
- In SG interrupt example set BD length to jumbo frame size.
- Fix interrupt ID generation for ZynqMP designs.
- In driver tcl improve error message for non-supported HW designs.
- Fix cppcheck and gcc warnings.
c676978 Fix error 'committing RxBD to HW' in SG dma interrupt example
3e6fd05 Fix interrupt ID generation for ZynqMP designs
fc025e0 Improve error message for non-supported HW designs
6b2c516 examples: Fix gcc [-Wint-conversion] warning
9711443 Include missing initializers for 'XAxiEthernet_Config' fields
2d15ad1 Fix cppcheck warnings
- Fix compilation issues in multicast/extvlan example.
- Set num of multicast table entries parameter based on hw design.
- Use table entries count from config structure.
- Used UINTPTR type for DMA BaseAddress.
- Implementing poll timeout API in the axiethernet driver.
axiethernet: Fix compilation issues in multicast/extvlan example5fa4d74
Set num of multicast table entries parameter based on hw designabe45ad
axiethernet: Use table entries count from config structureee523e1
axiethernet: Used UINTPTR type for DMA BaseAddress1866fc8
Axiethernet: Implementing poll timeout API in the axiethernet driver2017.4:2017.3
Commit ID's60104ac :
- Added support for Ethernet MCDMA Configuration in the driver
- Added axi ethernet mcdma examples.
- Fixed issues with Chipscope designs
- Fix pmufw compilation errors for Ethernet mcdma based designs.
axiethernet: Add support for mcdma2ad67e6 :
axiethernet: Add axiethernet mcdma examples14c3ca9 :
axiethernet: Fix issues with the chipscope designs2e47d70 :
axiethernet: Fix pmufw compilation errors2017.2
- Increase timeout values in the driver as per new h/w updates for ultrascale+ devices
Increase timeout values2017.1
Commit IDa523a1d :
- Added Support for TI PHY (DP83867)
Add Support for TI PHY in the peripheral test