UART standalone driver


Introduction

This page gives an overview of uartps driver which is available as part of the Xilinx Vivado and SDK distribution.
The UART controller is a full-duplex asynchronous receiver and transmitter that supports a
wide range of programmable baud rates and I/O signal formats. The controller can
accommodate automatic parity generation and multi-master detection mode.
The UART operations are controlled by the configuration and mode registers. The state of
the FIFOs, modem signals, and other controller functions are read using the status, interrupt
status, and modem status registers.
For more details, please refer zynqmp TRM which includes link s to the official documentation and resource utilization. 

Driver Sources

The source code for the driver is included with the Vitis Unified Software Platform installation, as well as being available in the Xilinx Github repository. 

Driver NamePath in VitisPath in Github
uartps<Vitis Install Directory>/data/embedded/XilinxProcessorIPLib/drivers/uartpshttps://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/uartps

Note: To view the sources for a particular release, use the rel-version tag in github.  For example, for the 2020.1 release, the proper version of the code is https://github.com/Xilinx/embeddedsw/tree/xilinx-v2020.1/XilinxProcessorIPLib/drivers/uartps

The driver source code is organized into different folders.  The table below shows the uartps driver source organization. 

Directory
Description

doc

Provides the API and data structure details

data

Driver .tcl and .mdd file

examples

Example applications that show how to use the driver features

src

Driver source files

Driver Implementation

For a full list of features supported by this IP, please refer zynqmp TRM which includes link s to the official documentation and resource utilization. 

Features

Programmable baud rate generator
64-byte receive and transmit FIFOs
Programmable protocol:
6, 7, or 8 data bits
1, 1.5, or 2 stop bits
Odd, even, space, mark, or no parity
Parity, framing and overrun error detection
Line-break generation and detection
Interrupts generation
RxD and TxD modes: Normal/echo and diagnostic loopbacks using the mode switch

The following features are supported in the uartps Standalone driver.
Loop UART 0 with UART 1 option
Modem control signals: CTS, RTS, DSR, DTR, RI and DCD are available only on the EMIO interface

Known Issues and Limitations

None

Example Applications

Refer to the driver examples directory for various example applications that exercise the different features of the driver. Each application is linked in the table below. The following sections describe the usage and expected output of the various applications.  These example applications can be imported into the Vitis IDE from the Board Support Package  settings tab. 


Test nameExample SourceDescription
Uart Interrupt examplexuartps_intr_example.cThis example does basic read and write test with interrupts.
Uart polled examplexuartps_polled_example.cThis example does basic read and write test using polling.
Uart hello world examplexuartps_hello_world_example.cThis example prints a string.

Example Application Usage

Uart Interrupt example

This example does basic read and write test with interrupts.

Expected Output

Successfully ran UART Interrupt Example Test

Uart polled example


This example does basic read and write test using polling.
Expected Output
Successfully ran UART Polled Mode Example Test

Uart hello world example


This example prints a string.
Expected Output
HelloWorld
Successfully ran Uartps hello world Example

Example Design Architecture

NA


2020.2


2020.1


2019.2


None

2019.1


None

2018.3