The AXI Quad Serial Peripheral Interface (SPI) core connects the AXI4 interface to those SPI slave devices that support the Standard, Dual, or Quad SPI protocol instruction set. This core provides a serial interface to SPI slave devices. The Dual/Quad SPI is an enhancement to the standard SPI protocol (described in the Motorola M68HC11 data sheet) and provides a simple method for data exchange between a master and a slave.
The source code for the driver is included with the Vitis Unified Software Platform installation, as well as being available in the Xilinx Github repository.
The driver source code is organized into different folders. The table below shows the nandpsu driver source organization.
Provides the API and data structure details
Driver .tcl and .mdd file
Example applications that show how to use the driver features
Driver source files
For a full list of features supported by this IP, please refer to Axi Quad Spi.
DMA access (aligned address only)
Configurable bus width
Interrupts – will be chosen and enabled internally
Known Issues and Limitations
The standalone driver supports Axi-spi and AXI Quad spi
Supported Flash vendors
Refer to the driver examples directory for various example applications that exercise the different features of the driver. Each application is linked in the table below. The following sections describe the usage and expected output of the various applications. These example applications can be imported into the Vitis IDE from the Board Support Package settings tab