Introduction

The XilFPGA library provides an interface for the users to configure the programmable logic (PL) from PS. The library is designed to run on top of Xilinx® standalone BSPs. It acts as a bridge
between the user application and the PL device. It provides the required functionality to the user application for configuring the PL device with the required bitstream.

Library Sources

The source code for the driver is included with the Vitis Unified Software Platform installation, as well as being available in the Xilinx Github repository.

Library Name	Path in Vitis	Path in Github
Xilfpga	<Vitis Install Directory>/data/embedded/lib/sw_services/xilfpga_v6_6	https://github.com/Xilinx/embeddedsw/tree/master/lib/sw_services/xilfpga

The driver source code is organized into different folders. The table below shows the axidma driver source organization.

Directory	Description
Doc	Provides the API and data structure details
data	Library .tcl, .mld and .yaml file
examples	Example applications that show how to use the driver features
src	Library source files

Note: The .yaml(in data folder) and CMakeLists.txt(in src folder) files would be used in the System Device-tree based flow.

Library Implementation

For a full list of features supported by this library, please refer to the xilfpga Doc

Features

The following features are supported in Zynq UltraScale+ MPSoC platform:

Full bitstream loading
Partial bitstream loading
Encrypted bitstream loading
Authenticated bitstream loading
Authenticated and encrypted bitstream loading
Readback of configuration registers
Readback of configuration data

The following features are supported in Versal platform:

Full/Partial bitstream loading
Device Key Encrypted bitstream loading
Authenticated bitstream loading
Authenticated and Device-key encrypted bitstream loading

Known Issues and Limitations

Example Applications

Refer to the driver examples directory for various example applications that exercise the different features of the driver.

Each application is linked in the table below. The following sections describe the usage and expected output of the various applications.

These example applications can be imported into the Vitis IDE from the Board Support Package settings tab.

Links to Examples

Examples Path: https://github.com/Xilinx/embeddedsw/tree/master/lib/sw_services/xilfpga/examples

Test Name	Example Source	Description
Full Bitstream/PDI loading	xfpga_load_bitstream_example.c	Transfer the user provided Full Reconfiguration Bitstream into the PL.
Partial Bitstream/PDI loading	xfpga_partialbitstream_load_example.c	Transfer the user provided Partial Reconfiguration Bitstream into the PL region
Readback of configuration registers	xfpga_reg_readback_example.c	This example prints out the values of all the configuration registers related to FPGA
Readback of configuration Data	xfpga_readback_example.c	This example prints out the fpga configuration data

Example Application Usage

Full Bitstream/PDI loading

Transfer the user provided Full Reconfiguration Bitstream into the PL.

Expected Output

Loading Bitstream for DDR location :0x80000
Trying to configure the PL ......
PL Configuration done successfully

Partial Bitstream/PDI loading

Transfer the user provided Partial Reconfiguration Bitstream into the PL Region.

Expected Output

Loading Partial Reconfiguration Bitstream from DDR location :0x80000
Trying to configure Partial Reconfiguration Bitstream into the PL ......
Partial Reconfiguration Bitstream loaded into the PL successfully

Readback of configuration registers

This example prints out the values of all the configuration registers related to FPGA

Expected Output

Register Read back example
Value of the Configuration Registers.
CRC ->   0 
FAR ->   7fc0000   
FDRI ->      0 
FDRO ->      effffffe  
CMD ->   d 
CTRL0 ->     101   
MASK ->      0 
STAT ->      16907ffc  
LOUT ->      0 
COR0 ->      38003fe5  
MFWR ->      0 
CBC ->   0 
IDCODE ->    1484a093  
AXSS ->      0 
COR1 ->      400000    
WBSTR ->     0 
TIMER ->     0 
BOOTSTS ->   1 
CTRL1 ->     0
Successfully ran Register Read back example

Readback of configuration Data

This example prints out the fpga configuration data.

Expected Output

FPGA Configuration data Read back example
0000 00000 00000 0000 0000
.... ..... ..... .... ....
.... ..... ..... .... ....
.... ..... .... .... ....
Successfully ran FPGA Configuration Read back example

Performance

N/A

Xilinx Wiki

Xilfpga

Introduction

Library Sources

Library Implementation

Features

Known Issues and Limitations

Example Applications

Example Application Usage

Full Bitstream/PDI loading

Partial Bitstream/PDI loading

Readback of configuration registers

Readback of configuration Data

Performance

ChangeLog

Related Links