Document History

Overview

This Tech tip explains the Ethernet debugging and benchmarking methods using the Zynq-7000 AP SoC
Zynq-7000 AP SoC has an in-built dual Giga bit Ethernet controllers which can support 10/100/1000 Mb/s EMAC configurations compatible with the IEEE 802.3-2008 standard. The Programming Logic (PL) sub system of the Zynq-7000 AP SoC can also be instantiated with the additional soft AXI EMAC controllers if the end application requires more than two Giga bit Ethernet Controller.
This techtip describes the step to use the PING utility, Wireshark network protocol analyzer, iperf and Netperf benchmarking tools. To follow these steps users can use the pre-built images available at following Xilinx resources:

1. Zynq-7000 IEEE1588 PTP Design
2. XAPP1026 - Zynq-7000 AP SoC Baremetal Reference Design
3. XAPP1082 -Zynq-7000 Linux Ethernet Reference Design

This tech tip explains the following sections:

1. Creating the design for Zynq-7000 AP SoC with Ethernet using the Vivado and SDK
2. Using the PING and traceroute utility
3. Basic troubleshooting techniques for the link establishment
4. Using the Wireshark network protocol analyzer
5. NetPerf benchmarking utility for Linux based solution
6. Iperf benchmarking utility for baremetal solution

Implementation

Creating the design for Zynq-7000 AP SoC with Ethernet using the Vivado and SDK

To follow the steps of trouble shooting and benchmarking you can also use the prebuilt images available in the above links or users can create their own design using the following procedure. If you want to run the prebuilt images then follow the procedure explained in the respected design and jump to the section ‘Using the PING utility’

Step by Step Instructions

List all the steps to run the design. This includes hardware, software and tools needed.

1. Launch Vivado IDE Design Tool: Vivado 2015.1 or latest
   On Windows 7, select Start > All Programs > Xilinx Design Tools > Vivado 2015.1 > Vivado 2015.1

On Linux, enter Vivado at the command prompt
2. Select “Create New Project” in launch window as shown in Figure 1 and new Vivado project wizard will open.
3. In the Create a New Vivado Project window gives summary of further steps, click Next
4. In the Project Name dialog box, type the project name (e.g. Zynq_PS_GEM) and location. Ensure that Create project subdirectory is checked, and then click Next.
5. In the Project Type dialog box, select RTL Project and ensure that Don’t specify the sources at this time is checked then click Next.
6. In the Default Part dialog box select Boards and choose ZYNQ-7 ZC702 Evaluation Board or ZYNQ-7 ZC706 Evaluation Board. Make sure that you have selected the proper Board Version to match your hardware because multiple versions of hardware are supported in the Vivado IDE. Click Next.
7. Review the project summary in the New Project Summary dialog box before clicking Finish to create the project. Project summary window similar to Figure 2 will be opened
8. In the Project Manager wizard under IP Integrator select Create Block Design, enter the design name or leave default (design_1) in the Please specify name of the block design pop-up window and select ok
9. In the desing_1 drawing view select Add IP as shown in Figure 3 and select Zynq7 Processing System in the next pop-up search window
10. Select Run Block Automation and /processing_system7_0 as shown in Figure 4