This page is outdated and in the archive state. For updated related content, please reference the following:
This page shows how to create a design to simulate a Master full AXI4 interface to validate it. The IP validated is the IP created in this wiki page
. To validate the AXI4 interface, we will use the AXI Verification IP which can simulate AXI4, AXI4-Lite and AXI3 interfaces. It also gives errors if there are issues with the interface (i.e. the interface does not comply with the AXI specification).
Table of Contents
Step 1 : Create a new Vivado 2017.1 project
Open Vivado 2017.1 and create a new project targeting the Xilinx ZC702 board
Step 2 : Add the custom IP to the IP repository
In vivado 2017.1, click on Tools > Settings > IP > Repository and add the path to the IP.ip_repo.zip
Step 3 : Create the Block Design
Create a block Design and add the custom IP (myAXI4IP). Configure the custom IP (myAXI4IP) by setting the Slave Base Address to 0x00000000. Then add an AXI Verification IP (AXI VIP). And configure it as a Slave. It will act like a memory.
We can note the following lines in the bottom of the VIP GUI:
Connect the Master AXI4 interface of the IP to test to the slave interface of the VIP.
Right click on the ports aclk and aresetn of the VIP and click Make External. Connect the ports m00_axi_aclk and m00_axi_aresetn of the custom IP to these external ports.Right click on the port m00_axi_init_axi_txn of the custom IP and click Make External.
In the address editor tab, map the VIP to the address 0x00000000
Validate the design, create the HDL wrapper and generate the BD output products.
Step 4 : Create the Test Bench
Create a new simulation source file of type systemVerilog (the VIP only works with systemVerilog).
Edit the file as following:
1. Add the required packages as mentioned in the VIP GUI:
2. Declare the test bench signals:
3. Instantiate the BD:
bit aclk = 0;
always #5ns aclk = ~aclk;
. aclk (aclk),
. m00_axi_init_axi_txn (pulse_inp)
Declare the agent for the VIP (one agent for one AXI VIP has to be declared). We want the VIP to act as a Slave with a memory model. Thus the type of the agent will be <component_name>_slv_mem_t.
// Declare agent
5.Create a procedural block with the following:
- Create a new agent and pass the hierarchy path of IF correctly into the new function
- Set a tag for agents for easy debug
- set print out verbosity level for the agent
- Start the agent
//Create an agent
slv_mem_agent = new("slave vip agent",DUT.design_1_i.axi_vip_0.inst.IF);
// set tag for agents for easy debug
// set print out verbosity level.
//Start the agent
Then create the stimuli for the IP:
aresetn = 1;
pulse_inp = 1;
pulse_inp = 0;
aresetn = 1;
The full test bench file is given here:
Step 5 : Launch the simulation
Run the simulation for 70us.
In the TCL console, the VIP gives information on the AXI transactions done:
The simulation does not stop on an error (in the TCL console), thus the interface seems to follow the AXI specification.
We can also add the AXI signals in the waveform window to see the AXI transactions: