The Zynq Programmable Logic (PL) can be programmed by the First Stage Bootloader (FSBL), U-Boot or through Linux. Programming the PL at different stages may be advantageous for different projects and workflows.
HW IP Features
It support full-bitstream and partial Bitstream loading.
It support Encrypted and Authenticated Bitstream loading.
Features supported in driver
It supports full-bitstream Bitstream loading.
Known Issues and Limitations
No support for partial Bitstream loading.
No support for Authenticated Bitstream loading.
No support for Encrypted Bitstream loading.
Device Drivers ---> Character devices ---> <*> Xilinx Device Configuration
Once booted into Linux, write the bitstream file to the devcfg device: Programming the PL through the FSBL The First Stage Boot-Loader (FSBL) is capable of programming the PL before loading U-Boot, which may be necessary for some applications. To have the FSBL load the PL, include the bitstream file when generating boot.bin and boot normally. References: