The xilinx_devcfg.c driver was deprecated in the 2018.1 release and FPGA manager support was added for the Zynq-7000 platform. The xilinx_devcfg.c driver was implemented with a character driver model that only supported Bitstream loading using the sysfs interface. It does not support the more advanced functionality supported by the FPGA Manager framework. Current designs should use Zynq FPGA manager to program the Bitstream for Zynq-7000.
The Zynq Programmable Logic (PL) can be programmed by the First Stage Bootloader (FSBL), U-Boot or through Linux. Programming the PL at different stages may be advantageous for different projects and workflows.
HW IP Features
It support full-bitstream and partial Bitstream loading.
It support Encrypted and Authenticated Bitstream loading.
Features supported in driver
It supports full-bitstream Bitstream loading.
Known Issues and Limitations
No support for partial Bitstream loading.
No support for Authenticated Bitstream loading.
No support for Encrypted Bitstream loading.
Device Drivers ---> Character devices ---> <*> Xilinx Device Configuration
Once booted into Linux, write the bitstream file to the devcfg device:
$cat bitstream.bit > /dev/xdevcfg
Programming the PL through the FSBL The First Stage Boot-Loader (FSBL) is capable of programming the PL before loading U-Boot, which may be necessary for some applications. To have the FSBL load the PL, include the bitstream file when generating boot.bin and boot normally. References: