The wiki page describes the tools that can be used to estimate and monitor the power consumption of ZynqMP and Versal while performing different scenarios in the Processing section (PS) as well as Programmable logic (PL). By executing these scenarios on both the PS and PL, users can use the actual power consumption information to predict the Power budget of their real application.
This page also describes various ways to optimize the power at different stages of the boot process, and links to a guide on debugging issues related to power management.
Tools to Estimate and Measure Power
Power estimation is critical for many decisions during the FPGA design process—from device selection to system-level power budgeting and thermal design. Power Design Manager (PDM) is the new, next-generation power estimation platform designed to bring accurate and consistent power estimation capabilities to even the largest Versal and Kria SOM products. Power Design Manager is the preferred power estimation tool for the Versal product family. XPE will continue to support all devices prior to the Versal product family.
The Xilinx Power Estimator (XPE) is a spreadsheet-based tool that helps you to achieve this. XPE estimates the power consumption of your design at any stage during the design cycle. It accepts design information through simple design wizards, analyzes them, and provides detailed power and thermal information.
The Jupyter notebook-based Power Advantage tool (PAT) and BEAM tool can be used to monitor and modify different parameters (clocks, voltages, power, etc.) on the evaluation boards. The BEAM tool is targeted for the Versal platforms whereas PAT is targeted for the ZynqMP platforms.
RAFT is a non-system controller-based Python toolbox which provides direct access to FPGA hardware peripherals. RAFT runs in PetaLinux and provides access to various C driver library APIs through Python.
This tool uses the internal implementations of Jupyter notebook based power advantage tool but it uses the regular PS Ethernet port instead of the system controller to monitor the power. We can find the relevant GitHub page that describes its usage here https://github.com/Xilinx/RAFT
Board Design Considerations for Power Management
It is best practice to group multiple rails into a single power supply source to optimize the overall cost of the board or control I/Os. However, for applications requiring fine-grain power control and use cases where certain power domains can be powered-off for significant durations of time, it is essential to have independent power supply controls for LPD, FPD, and PLD.
Xilinx/pm_demo (github.com) repository contains the source code needed to recreate, modify, and extend the DFx boot power demo to demonstrate Versal/ZynqMP device's various power modes
Linux Power Management
Both Zynq UltraScale+ and Versal provide ways to test its various PM features through the SW mechanism such as in the Linux Kernel. Test steps describing the PM features in the Linux including Runtime suspend/resume and the various wake-up sources outlined here: https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842232
Typical Power States
We can measure transition times and respective power values when either the PS or PL suspends or wake up. The https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/1078460507 page describes the various ways through which the user can see/measure the suspend/wake-up time and power. These procedures are for 2020.2 and later releases.
For PL Designs, different implementation options are presented by Vivado, including Optimization for Power. For designs targeting low power, this setting needs to be selected. It is typical to be able to save up to 30% of the PL power this way, depending on the design contents. Here is a snapshot of the selection in the “Implementation Settings” dialog.
More detailed instructions are covered by these guides provided by Xilinx:
To enable runtime power management, there are several techniques that need to be employed in defining controls for clocks and power modes of PL IPs. These techniques are explained in detail on this page: https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/1433960485. It is typical to be able to save 40% of the PL power this way.
PM with Custom Software Stack
For applications that use a custom software stack that cannot leverage the AMD provided power management framework or are not interested in active runtime power management, but still looking for an efficient low-power design, here are a few techniques that might be useful: