Power Management - Getting Started

This page acts as a landing page for users to get started with power management targeting Zynq UltraScale+ and Versal Adaptive SoCs.

Table of Contents


The wiki page describes the tools that can be used to estimate and monitor the power consumption of ZynqMP and Versal while performing different scenarios in the Processing section (PS) as well as Programmable logic (PL). By executing these scenarios on both the PS and PL, users can use the actual power consumption information to predict the Power budget of their real application.

This page also describes various ways to optimize the power at different stages of the boot process, and links to a guide on debugging issues related to power management.

Tools to Estimate and Measure Power


Power estimation is critical for many decisions during the FPGA design process—from device selection to system-level power budgeting and thermal design. Power Design Manager (PDM) is the new, next-generation power estimation platform designed to bring accurate and consistent power estimation capabilities to even the largest Versal and Kria SOM products. Power Design Manager is the preferred power estimation tool for the Versal product family. XPE will continue to support all devices prior to the Versal product family.

More information on the PDM can be found here https://www.xilinx.com/products/design-tools/power-design-manager.html


The Xilinx Power Estimator (XPE) is a spreadsheet-based tool that helps you to achieve this. XPE estimates the power consumption of your design at any stage during the design cycle. It accepts design information through simple design wizards, analyzes them, and provides detailed power and thermal information.

More information on XPE and its usage can be found here https://www.xilinx.com/products/technology/power/xpe.html

System Controller based power monitoring

https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/2273738753 Provides generic details on the System controller on Versal.

The Jupyter notebook-based Power Advantage tool (PAT) and BEAM tool can be used to monitor and modify different parameters (clocks, voltages, power, etc.) on the evaluation boards. The BEAM tool is targeted for the Versal platforms whereas PAT is targeted for the ZynqMP platforms.

  1. Here you can find the example using the BEAM tool to monitor the power and . A brief description of the Versal power tool is also outlined here for a better understanding

  2. The power Advantage tool can also be used to monitor the overall system power consumption and the steps to use the same are here:

  3. Source code repositories for these system controller based tools can be found here:

  4. PetaLinux provides the system controller packages as part of its build system and you find these utilities as part of PetaLinux here: . We can use also use the sc_app command line utility of PetaLinux to monitor the power against the respective voltage rails

RAFT (Rapid Abstraction FPGA Toolbox)

RAFT is a non-system controller-based Python toolbox which provides direct access to FPGA hardware peripherals. RAFT runs in PetaLinux and provides access to various C driver library APIs through Python.

This tool uses the internal implementations of Jupyter notebook based power advantage tool but it uses the regular PS Ethernet port instead of the system controller to monitor the power. We can find the relevant GitHub page that describes its usage here

Board Design Considerations for Power Management

It is best practice to group multiple rails into a single power supply source to optimize the overall cost of the board or control I/Os. However, for applications requiring fine-grain power control and use cases where certain power domains can be powered-off for significant durations of time, it is essential to have independent power supply controls for LPD, FPD, and PLD.

The cover specific PM-related design guidelines that need to be considered to enable proper runtime power management targeting the Zynq UltraScale+ platform

Power Management Software Solutions

Power Management Demo

Xilinx/pm_demo (github.com) repository contains the source code needed to recreate, modify, and extend the DFx boot power demo to demonstrate Versal/ZynqMP device's various power modes

Linux Power Management

Both Zynq UltraScale+ and Versal provide ways to test its various PM features through the SW mechanism such as in the Linux Kernel. Test steps describing the PM features in the Linux including Runtime suspend/resume and the various wake-up sources outlined here:

Typical Power States

We can measure transition times and respective power values when either the PS or PL suspends or wake up. The page describes the various ways through which the user can see/measure the suspend/wake-up time and power. These procedures are for 2020.2 and later releases.

Suspend-Resume Baremetal Use-case

Here you can find the Suspend-resume example in XilPM client Library ( runs on APU/RPU): https://github.com/Xilinx/embeddedsw/blob/master/lib/sw_services/xilpm/examples/xilpm_selfsuspend_example.c

Software Support for Power Management contains more tips and examples of power management solutions for Zynq UltraScale+ MPSoC , RFSoC and the Versal Adaptive SoC Core, Prime, and Premium devices.

Power Optimization Techniques

The section is inherited from the Power Optimization Guide for Zynq UltraScale+ MPSoC

PS Design Optimizations

The PS side of the design optimizations to save power involves disabling unused blocks, optimizing clocks, DDR configurations, etc. The PS has power islands that can be power gated to eliminate static power consumed by that island. Power gating is handled by the PM framework automatically at runtime. The PM framework depends on the configuration specified in Vivado to power down unused blocks. So it is essential to properly specify which blocks are used/unused to get the power savings. It is typical to be able to save 20% of the PS power this way. Listed here are the ways to optimize the power: , , and

PL Design Optimizations

For PL Designs, different implementation options are presented by Vivado, including Optimization for Power. For designs targeting low power, this setting needs to be selected. It is typical to be able to save up to 30% of the PL power this way, depending on the design contents. Here is a snapshot of the selection in the “Implementation Settings” dialog.

More detailed instructions are covered by these guides provided by Xilinx:

UG907 and UG786

To enable runtime power management, there are several techniques that need to be employed in defining controls for clocks and power modes of PL IPs. These techniques are explained in detail on this page: . It is typical to be able to save 40% of the PL power this way.


PM with Custom Software Stack

For applications that use a custom software stack that cannot leverage the AMD provided power management framework or are not interested in active runtime power management, but still looking for an efficient low-power design, here are a few techniques that might be useful:

Power Management Debugging Techniques

There may be a need to debug or explore the power, clock, and reset states of various blocks on the SoC. describes the various strategies to help debug such PM issues with Zynq UltraScale+ devices.

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