Zynq-7000 AP SoC - Read and Write to the Zynq OCM from The PL

Introduction

This article shows how to create an IP with a master full AXI4 interface used to read and write from the Programmable Logic (PL) to the On-Chip Memory (OCM) of the Processing System (PS) using the zynq S_AXI_HP0 slave interface. It uses Vivado/SDK 2017.1 and targets a ZC702 board.

Step 1 : Create a new Vivado 2017.1 project

Open Vivado 2017.1 and create a new project targeting the Xilinx ZC702 board

Step 2 : Create an new IP with a master full AXI4 interface

In Vivado 2017.1, click on Tools > Create and Package New IP. Create a nex AXI4 peripheral called myAXI4IP.

On the Add Interfaces page, add a new 32-bit master full AXI4 Interface




Then package the IP without editing it.
Vivado as generated a template for the IP. The IP will write data to the SLAVE_BASE_ADDRESS (entered when configuring the IP) and then read the data back to check that the write was successful. The data written should be 0x1,0x2...0xn to the addresses SLAVE_BASE_ADDRESS, SLAVE_BASE_ADDRESS + 0x4 ... SLAVE_BASE_ADDRESS 0x4*n (with n the burst length entered when configuring the IP).

We could check validate the functionality of the IP in simulation with the AXI VIP (this is shown in this wiki page)

Step 3 : Create the Vivado design

As per the UG585:
"The four AXI_HP interfaces (from the PS) provide PL bus masters with high bandwidth datapaths to the DDR and OCM memories."
So in this part we will connect the newly created IP to the zynq S_AXI_HP0 slave interface

In the main project, create a new Block Design (BD) and add a Zynq-7.
In the Zynq-7 GUI, load the preset configuration for the ZC702 board. Then in the PS-PL configuration page, enable the S_AXI_HP0 slave interface: