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Table of Contents
This page provides introduction to System Monitoring application note including steps on how to build various related hardware/software components and setup the hardware platform and run the design on the ZC702 Evaluation Kit
. The ZC702 Evaluation kit is based on a XC7Z020 CLG484-1 Zynq-7000 SoC
device. For additional information, refer to XAPP1182
1.1 Design Description
The Zynq-7000 family is based on the Xilinx SoC architecture. These products integrate a feature-rich dual-core ARM Cortex-A9 based processing system (PS) and 28 nm Xilinx programmable logic (PL) in a single device. The ARM Cortex-A9 CPUs are the heart of the PS and include on-chip memory, external memory interfaces, and a rich set of peripheral connectivity interfaces.The Zynq-7000 AP SoC PS can establish connectivity to the XADC, an integrated 12-bit,17-channel, 1 MSPS analog-to-digital converter using the AXI interface when the XADC is instantiated in the PL. The XADC is an embedded block offered in all Zynq-7000 SoC devices.The LogiCORE™ XADC Wizard IP provides an AXI4-Lite compatible interface and an optional AXI4-Stream interface. The AXI4-Lite interface can be used to configure the XADC, and the AXI4-Stream interface can be used for data communication. The AXI4-Stream interface provides an option to interface the XADC data interface to other signal processing IP. This application note demonstrates the use of the AXI4-Lite interface for system monitoring applications using the XADC.
The XADC has a power supply and temperature sensor that can be used for system monitoring. Each of these sensors has configurable minimum and maximum threshold limits.When the measured physical parameter (voltage or temperature) crosses the threshold condition, an alarm signal is asserted. For more details on the on-chip sensors, see 7 Series FPGAs and Zynq-7000 SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter User Guide (UG480) [Ref 1].Xilinx provides an Industrial Input/Output (IIO) framework-based Linux driver which acts as a device driver for the XADC applications that use the AXI interface. The driver can configure the XADC for various operating modes, collect data from XADC, and make data available in the user space layer.For more details on XADC please refer chapter 30 of Zynq-7000 TRM (ref link).The focus of this application note is to showcase system monitoring feature of Zynq-7000 devices implemented using dedicated XADC to PS interface.Key highlights of this application note are:
- Showcases how to quickly establish an interface between Zynq-7000 XADC using AXI interface.
- Example code for System Monitoring.
- Evaluate the XADC’s performance using AXI interface.
2 Package Content
The XAPP1182 package
contains the following:
The following Figure represent application note directory structure tree.
- XAPP1182 Linux Software based Application C code for command line
- Webserver based Linux application project
- Common library / XADC core implementation
- Pre-built SD images for out-of-box user experience
- Readme file
3 Prerequisites It is assumed that the unzipped package is available at $ZYNQ_XADC_PL_HOME. Create workspace directory inside $ZYNQ_XADC_PL_HOME directory for development area.
4 Build Hardware components
Follow the below steps to build the Hardware design
1. Browse to
2. Type the below command on Linux/Windows command line:
bash> vivado -source axi_xadc_gui.tcl
The above step will open Vivado GUI and the project.
3. Click on Generate Bitstream option which generates the bitstream
4. Go to File-> Export -> Export Hardware for SDK option and click OK
5 Build software components
5.1 Standard ZYNQ software components
- Includes creation of FSBL (First Stage boot loader) . FSBL used in the application note is based on zc702_hw_platform(predefined).
- Building of FPGA Hardware bitsream using Xilinx Vivado™ Design Suite
- Building Xilinx configured uboot (Second stage boot loader) for zc702 board. Check out tag "xilinx-v14.5" and follow standard uboot build process.
- Create BOOT.bin (zynq_fsbl.elf ,system.bit and u-boot.elf)
Building standard software/hardware components are not covered in this application note and avoided for simplicity.
User may refer to detail build steps mentioned in Zynq Base TRD 14.5
wiki which are identical to this application note requirements.
5.2 Building the Linux Kernel
A pre-compiled Linux kernel can be found at $ZYNQ_XADC_PL_HOME/ready_to_test/uImage.
Set the CROSS_COMPILE environment variable and add it to your PATH.
bash> export CROSS_COMPILE=arm-xilinx-linux-gnueabi-
bash> export PATH=/path/to/cross/compiler/bin:$PATH
Linux kernel compilation internally uses mkimage command for creating uImage (Linux Kernel Image).
One can use the mkimage command that is built during u-boot building process (Section 4.1).
Note: It is assumed that user has cloned/build u-boot inside $ZYNQ_XADC_PL_HOME/workspace directory.
bash> export PATH=$ZYNQ_XADC_PL_HOME/workspace/u-boot-xlnx/tools:$PATH
Clone the latest Zynq Linux kernel git repository from the Xilinx git server
bash> cd $ZYNQ_XADC_PL_HOME/workspace
bash> git clone git://github.com/Xilinx/linux-xlnx.git
Create a new branch named zynq_xadc_pl based on the xilinx-v14.5.01.
bash> cd $ZYNQ_XADC_PL_HOME/workspace/linux-xlnx
bash> git checkout -b zynq_xadc_pl xilinx-v14.5.01
Apply the App note specific patch on top of the xilinx-14.5.01 tag. The patch includes:
- Customization to IIO framework and Xilinx IIO ADC based driver.
Configure the Linux kernel for the this app note by including iio based driver [ Also by excluding hwmon based xadc driver]
bash> cp $ZYNQ_XADC_PL_HOME/software/patches/zynq_pl_xadc.patch . // Copy the patch from package to development area
bash> git apply --stat zynq_pl_xadc.patch // Display stat of patch content.
bash> git apply --check zynq_pl_xadc.patch // Check if patch can be applied
bash> git am zynq_pl_xadc.patch // Apply the patch
Build the Linux kernel. The generated kernel image can be found at $ZYNQ_XADC_PL_HOME/workspace/linux-xlnx/arch/arm/boot/uImage.
bash> make ARCH=arm zynq_iio_xadc_defconfig
bash> make ARCH=arm uImage modules UIMAGE_LOADADDR=0x8000
5.3 Building the Linux Device Tree Blob
This step requires that the previous steps are completed. A pre-compiled Device Tree Blob can be found at $ZYNQ_XADC_PL_HOME/ready_to_test/devicetree.dtb.Compile the device tree source using dtc tool.
bash> ./scripts/dtc/dtc -I dts -O dtb -o devicetree.dtb $ZYNQ_XADC_PL_HOME/software/devicetree/zynq-zc702-pl-xadc.dts
6 Hardware Setup Requirements
1. The ZC702 evaluation board
with the XC7Z020 CLG484-1 part2. XAPP1182 zip file containing the design source files and application binaries.
2. Internet Explorer version 8.0 or aboveAMS101 evaluator card.
3. Optional signal generator to test externally applied analog signal.
4. Mini USB cable.
5. Class 4 equivalent SD card.
6. A control PC.
7 Execution Steps
This section summarizes the execution steps of the XAPP on ZC702 platform.
7.1 ZC702 Initial Setup
1. All jumpers and switches should be in default setting except SW16.
Mode switch SW16 should be set to boot from SD card.
Use the following switch settings:
2. Connect the AC power adapter
3. If USB-to-UART bridge is used, connect USB Mini-B side of USB-to-Mini-B cable to the on-board mini USB connector (J17). Connect USB side to the control PC.
4. Install SVG Viewer
5. Connect ethernet cable between Host PC and the Zynq Board via RJ45 cable. Make sure Host PC and Zynq are in same network domain.
Note: For static IP (through dts), the zynq having IP as 192.168.1.10; the host PC can have IP address 192.168.1.2
7.2 Webserver execution steps
1. Load the SD card with content of <pkg>/read_to_test. Insert this SD card in zynq board.
2. Power ON the zynq board and wait for few minutes
-- see the Linux booting in the uart terminal
-- After power up, the webserver starts automatically on background through init script.
3. On Host machine open IE 8(or above) browser.
4. Type zynq ip with port number 9090 in the address bar of browser.
-- e.g. http://192.168.1.10:9090
5. Observe the senor values / graphs on the web page.
6. Change threshold values to see the Alarm triggering and status change.