Zynq-7000 AP SoC - Performance - Ethernet Packet Inspection - Bare Metal - Redirecting Packets to PL Tech Tip

Document History

Introduction

The technical tip described here explains how the Ethernet packet received by the Gigabit Ethernet Interface on the Zynq Processing System can be diverted to the PL for packet inspection. The design used in this tech tip basically comprises of Block RAMs implemented in PL that accepts packets from the PS Ethernet Controller. This design can form the basis for a Hardware Packet Inspection engine that can be implemented in PL.

Designers interested in Packet filtering or Deep packet Inspection of Ethernet Packet can refer to this design to redirect Zynq PS Ethernet data to PL for Hardware Inspection.The concept or theory explained in this tech tip not only applies to PS Ethernet Controller but also can be equally applied for any high speed peripheral having its own DMA controller in the Zynq Processing System.

The design used in this tech tip has been implemented and tested on a ZC702 board.

The design files for this tech tip is located here : Zynq7000AP_SoC_Ethernet_Packet_Redirection_Design.zip
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Ethernet Data Movement in Zynq Processing System

The Gigabit Ethernet MAC Controller on Zynq Processing System comprises of three blocks.

1. MAC Controller

2. FIFO(Packet Buffer)

3. Ethernet DMA Controller

The Ethernet DMA controller is attached to the FIFO to provide a scatter-gather type capability for packet data storage in a Zynq processing system.The Ethernet DMA uses separate transmit and receive lists of buffer descriptors, with each descriptor describing a buffer area in memory. This allows Ethernet packets to be broken up and scattered around the AXI memory space. The data received by the controller is written to pre-allocated buffer descriptors in system memory. These buffer descriptor entries are listed in the receive buffer queue. The Receive-buffer Queue Pointer register of the Ethernet DMA points to this data structure on initialization and uses it to continuously and sequentially to copy the Ethernet packet received in the Ethernet FIFO to Memory address specified in the receive buffer queue.

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Figure 1: Rx Buffer Queue Structure

In case of Transmit, the data to be transmitted is read from buffers present in system memory. These buffers are listed in the transmit buffer queue. The Transmit Buffer Queue Pointer register of the DMA points to this data structure on initialization and uses it to continuously transmit packets that has been assembled in the address specified in the buffer descriptor present in the transmit buffer queue. More information on the RX and TX Buffer descriptor can be read from the “16.3.5 Configure the Buffer Descriptors “section in the Zynq-7000 Technical reference manual(UG585). As described above, in the current Zynq Processing System the Transmit and receive buffer descriptors are initialized in the Ethernet driver before the Ethernet Hardware is enabled in the software.
When an Ethernet Packet is received, the Ethernet DMA uses the address in the RX Buffer descriptor to push the packet that has been buffered in the Packet Buffer on Ethernet interface to DDR3 memory, via the central interconnects. In this case the data is not cached and is directly passed on the DDR3 memory.

In case of transmit the Ethernet DMA uses the address in the TX Buffer descriptor to pull data from DDR3 Memory, through the central interconnect and finally to the ETH0 Interface.

1. Data Receive Path: ETH0 à ETH0 DMA (32-bit)à Central Interconnectà DDR3 Memory Controller (64-bit AXI).

2. Data Transmit path: DDR3 Memory Controller (64-bit AXI) à Central Interconnectà ETH0 DMA (32-bit) àETH0

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Figure 2: Ethernet Data Movement

Implementation