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Zynq-7000 AP SoC - 32 Bit DDR Access with ECC Tech Tip

Zynq-7000 AP SoC - 32 Bit DDR Access with ECC Tech Tip

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Sept 24, 2018

Zynq-7000 AP SoC - 32 Bit DDR Access with ECC Tech Tip

Document History

Date
 Version
 Author
 Description of Revisions
23/06/14
 0.1
 Yashu Gosain
 Initial revision

Summary

As technology is evolving, dynamic random-access memory (DRAM) device size increases and components on chips get smaller, due to that DRAM chips becoming more affected by electrical or magnetic interference. Lower energy particles are able to change memory cell’s state. These kinds of interferences can cause a single bit of DRAM to spontaneously flip to the opposite state. It can lead system to either crash or to corruption of data.
Several approaches have been developed to deal with unwanted bit-flips. One of the approaches is to calculate an error-correcting code (ECC) for data and store it in DRAM along with data. The most common ECC, a SECDED Hamming code, allow a single bit error to be corrected and double bit errors to be detected.
Zynq-7000 SoC only offers 16 bit ECC on DRAM DDR devices which is only the half-bus (16-bit) data width DDR configuration. Several customers prefer to use a single DDR RAM at 32-bits width for data stored in DRAM, but require ECC for software storage in DRAM.
This Tech-tip intention is provide Zynq based system which supports 32 bit ECC access on DDR devices. It provides hardware IP which can be integrated in Zynq Programmable logic (PL) to support 32 bit ECC for DDR. It also provides detail about porting of Linux software on top it. User can use hardware IP integration and software porting details to get 32 bit ECC support for their system.

Implementation

Implementation Details
Design Type
 PS + PL
SW Type
 Linux
CPUs
 2 ARM Cortex-A9 667MHZ
PS Features
  • DDR3 533 MHZ
  • L2-Caches
  • UART
Boards/Tools
Xilinx Tools Version
 Vivado 2014.1
Board
 ZC702 Rev 1.0
Files Provided
ZYNQ7000AP_Soc_32bitDDRAcccesWithECC.zip
 See Appendix A for the descriptions of the files

Prerequisites

  • The ZC702 Evaluation Kit ships with the Xilinx Vivado™ Design Suite Device-locked to the Zynq-7000 XC7Z020 CLG484-1 device.
  • A Linux development PC with the ARM GNU tools installed.
  • A Linux development PC with the distributed version control system Git installed. For more information, refer to the Xilinx Git wiki and to UG821: Xilinx Zynq-7000 SoC Software Developers Guide.
  • A Linux development PC with PetaLinux SDK installed. For more information , refer to Xilinx PetaLinux user manuals.
  • Download design files (ZYNQ7000AP_Soc_32bitECCProxy.zip) from link provided above under Implementation details. Extract its content to Proxy home directory referred to as ZYNQ_PROXY_HOME in this document.
Refer Appendix A, for more details about the design files structure.


Description:


For Zynq to support 32 bit ECC on DDR device, a solution called “ECC Proxy” has been developed which adds ECC to selected address range in DDR. ECC Proxy block adds byte level ECC to each AXI transaction. With Byte level ECC, 1 ECC byte is used for each data byte which doubles the amount of read or writes data. Transactions protected by the ECC proxy will have increased latency because effective memory bandwidth is reduced. System level performance will be less affected since the primary usage is to load DDR data to L2 cache. Outside of the increased memory latency to protected regions of DDR, the use of ECC protection should be transparent to the system.

Application Processer unit (APU) of Zynq-7000 SoC normally accesses external DDR memory via L2 cache. All coherent access from APU goes through Snoop control unit (SCU) which in turn connected to L2-cache controller. There is dedicated port from L2- controller to DDR co