Document History

Description/Summary

A Single Chip Reference Design for Data Acquisition and DSP Signal Processing implementing a Spectrum Analyzer to demonstrate the capability of the Zynq-7000 AP SoC on the ZC702.



These instructions are for operating the demonstration design. No implementation is discussed in this Tech Tip. The implementation of the design is discussed in other Tech Tips.

This demonstration is based on the 2014.2 revision of the base TRD for the ZC702. It is assumed that the user is familiar with operation of the ZC702.

Implementation

Block Diagram

Overview

Single Chip Reference Design for Data Acquisition and DSP Signal Processing

12 bit 1 Mega-sample Per Second Data Acquisition via Integrated XADC
– Low Latency Sample Delivery Directly via DMA to Processor Cache

FFT Function Acceleration vs ARM alone Demonstrated Via:
– ARM Cortex-A9 NEON Instructions or
– Programmable Logic Based Xilinx Complex FFT Core

Low Latency and High Performance Data Passing between Processor and Programmable Logic via Accelerator Coherency Port

Graphical display output via HDMI

Available as Reference Design from Xilinx
.

Expected Results

Accelerate FFT with NEON Instructions or

Via Programmable Logic Coprocessor

4096 point FFT – Complex 32 bit floating point

• ARM processor alone – 830 usec
• NEON SIMD engine – 571 usec
• Hardware in PL fabric – 129 usec

Setup and Operation

Download the referenced SD card image file: ZC702FFTdemo2014dt3.zip

Requirements:

• ZC702
• Micro-USB to USB Hub Cable
• USB Hub
• USB Mouse (Keyboard is optional)
• 4GB or larger SD Card to hold design
• Optional to see boot process with USB-UART terminal
  • USB to Mini-USB for USB UART
  • PC
  • TeraTerm or equivalent terminal
    program installed on PC
• HDMI 1920 X 1080P display
• HDMI to HDMI cable
• Faster Technology XA-2 headphone adapter
• MP3 player / phone / tablet as signal source
• Headphone cable

Setup:

1. Setup per Photo Below

• Not required but shown
  • Ethernet
  • Serial port (USB UART)

1. Recommended but not shown
   • USB power adaptor for MP3 player & speaker
   • If used then USB hub not required
2. Optional
   • Keyboard w touchpad instead of mouse
   • Speaker attached to splitter from MP3 player and power from USB hub

Operation:

• Connect cables per instructions above
• Create bootable SD card from card image zip file
  • Download zip file from ZC702FFTdemo2014dt3.zip
  • Unzip image and copy files to blank SD card
• Set ZC702 switches to boot from SD card slot

• Set up input source using Faster Technology XA-2 headphone adapter

• Verify that jumper settings are set to defaults
  • J2 and J7 connected
  • J4 2 & 3 connected
  • J8 1 & 2 connected
• Insert XA-2 into XADC header
• Connect signal source (MP3 player, etc.) using standard 3.5 mm stereo cable as shown in setup photo
• Insert SD card into ZC702 and turn on power
• Demo will begin self running with defaults
  • Test Pattern Generator
  • Normal FFT Display
  • FFT Scale = 1 Volt Max
  • Sample Rate = 1 Msps
  • Hann Windowing
  • SW FFT computation
  • Normal compute

Controls:

Control Bar at top of display screen.



Operation of Controls


Play, Pause, Pause 5 seconds repeatedly



Click button to select Test Generator or External Data (XADC input)



Click to select 5X zoom of Frequency display (horizontal zoom) - Good for display of low frequency sources



Select vertical scale (maximum value) for FFT display - 0.1, 0.25, 0.5 or 1.0 volts - enhances low level signals



Sample Rate - select the sample rate for the input signal (20, 50, 100, 200, 500, 1000 K Samples / sec.)



Windowing function to apply to FFT - select None or a common FFT window function (http://en.wikipedia.org/wiki/Window_function)



FFT compute resource used - Software in ARM processor only, NEON SIMD, or PL Accelerated (See yellow status window for average compute time)



Compute Type - Normal / Multiple - multiple reads and computes 1000 FFTs and then displays the last computed value. This is useful for seeing relative update performance and CPU loading.

Information Displays:

Status Window - displays average compute time for the FFT - depends on FFT Type selected.



Performance - shows the CPU loading and use of the HP ports bewteen the PS and PL.



Block Diagram shows the data flow in the application - changes based on selected input and FFT Type.



Usage - graphically shows CPU and AXI bus loading

Conclusions:

This demonstration clearly shows the power of the Zynq 7000 AP Soc in action. Observers can see the FFT being performed and displayed and compare the different methods of performing the complex FFT calculations. The graphics are performed with the Qt system in conjunction with the hardware display controller used in the video base Targeted Reference Design, demonstrating the power of the Vivado / SDK development environment and compatibility with standard ARM / Linux system components that users might access in building their Zynq based systems.