This page show how to use the AXI4 VIP as a master to simulate read and write operation into a memory.
Table of Contents
Create the project
Open Vivado 2017.2 and create a new project (the target language of the project needs to be Verilog to use all the features of the VIP). Create a new block design (BD) and add an AXI4 Verification IP configured as Master with an AXI4-Lite Interface.
Make the port aclk and aresetn of the VIP external.
Add an AXI BRAM controller and configure it for AXI4-Lite protocol
Connect the AXI BRAM and the AXI VIP together and then click on Run Connection Automation. Select everything and click ok.
In the Address Editor tab, click on auto assign address to give an address to the AXI BRAM IP. In this case, the base address assigned is 0xC000_0000.
Save the BD and generate the output products and the wrapper for the BD.
Create the test bench for the design
Create a new simulation source file of type systemVerilog (the VIP only works with systemVerilog).
Edit the file as following:
1. Add the required packages as mentioned in the VIP GUI:
Create a new agent and pass the hierarchy path of IF correctly into the new function
Set a tag for agents for easy debug
set print out verbosity level for the agent
Start the agent
//Create an agent
master_agent = new("master vip agent",DUT.design_1_i.axi_vip_0.inst.IF);
// set tag for agents for easy debug
// set print out verbosity level.
//Start the agent
aresetn = 1;
6. Use the tasks AXI4LITE_READ_BURST and AXI4LITE_WRITE_BURST to send read and write commands