Using the AXI4 VIP as a master to read and write to an AXI4-Lite slave interface

Table of Contents



Create the project

Open Vivado 2017.2 and create a new project (the target language of the project needs to be Verilog to use all the features of the VIP). Create a new block design (BD) and add an AXI4 Verification IP configured as Master with an AXI4-Lite Interface.


Make the port aclk and aresetn of the VIP external.

Add an AXI BRAM controller and configure it for AXI4-Lite protocol


Connect the AXI BRAM and the AXI VIP together and then click on Run Connection Automation. Select everything and click ok.

In the Address Editor tab, click on auto assign address to give an address to the AXI BRAM IP. In this case, the base address assigned is 0xC000_0000.

Save the BD and generate the output products and the wrapper for the BD.

Create the test bench for the design

Create a new simulation source file of type systemVerilog (the VIP only works with systemVerilog).

Edit the file as following:

1. Add the required packages as mentioned in the VIP GUI:

2. Declare the test bench signals:

3. Instantiate the BD:

4. Declare the agent for the VIP (one agent for one AXI VIP has to be declared). We want the VIP to act as a Master. Thus the type of the agent will be <component_name>_mst_t

5.Create a procedural block with the following:
  • Create a new agent and pass the hierarchy path of IF correctly into the new function
  • Set a tag for agents for easy debug
  • set print out verbosity level for the agent
  • Start the agent

6. Use the tasks AXI4LITE_READ_BURST and AXI4LITE_WRITE_BURST to send read and write commands

7. Check that the write and read operations were successful (data match)
The full test bench file can be downloaded here:


Run the simulation

Launch the simulation. We can see that the write and read operations were successful in the waveform window (data_wr1 matches data_rd1 and data_wr2 matches data_rd2)

And in the console (message “Data match, test succeeded” printed)