Document History

Summary

The interrupt latency is the time elapse when an interrupt is generated to when the interrupt source is acted on i.e. duration between an interrupt generation/external event and CPU core branches to first instruction of the interrupt service routine. In real time systems, the interrupt latency plays a major role in the determinism and overall system response to a real time event. The interrupt latency depends on different factors like interrupt controller implementation, low level software architecture, operating systems, middle-ware stacks, device or peripheral specific interrupt handling requirements, priority of the interrupt and interrupt handler implementation.

The Zynq-7000 AP SoC has an inbuilt hardened interrupt controller called generic interrupt controller (GIC). The dual ARM Cortex A9 processing cores handle the generic peripheral interrupts in IRQ and FIQ modes. The GIC is a centralized resource for managing interrupts sent to the CPUs from the PS and PL. The controller enables, disables, masks, and prioritizes the interrupt sources and sends them to the selected CPU or both CPUs. In addition, the controller supports security extension for implementing a security-aware system.

This reference design and demo shows

1. The interrupt latency (max, min, ave and jitter) information for a PL peripheral interrupt
2. Using the Private Peripheral Interrupt (PPI) and Shared Peripheral Interrupt (SPI) interrupts
3. Different options like moving the ISRs to OCM, DDR, cached and non-cached memory locations etc in case of bare metal software
4. Creating the page faults to have a real time scenario and know the maximum/worst case interrupt latency with Linux OS

Implementation

This TechTip covers the following topics:

1. Zynq-7000 AP SoC Generic Interrupt Controller overview
2. Interrupt latency measurement design details
3. How to create the HW project using the Vivado tool
4. How to create the SW project for the: Linux AMP where Core 0 running Linux software, Core 1 running bare metal and FreeRTOS software
5. Running the Demo: Linux AMP with Baremetal/FreeRTOS interrupt latency demo

Zynq-7000 AP SoC Generic Interrupt Controller Overview

The Generic Interrupt Controller (GIC) is a centralized resource for managing interrupts sent to the CPUs from the PS and PL. The controller enables, disables, masks, and prioritizes the interrupt sources and sends them to the selected CPU (or CPUs) in a programmed manner as the CPU interface accepts the next interrupt. In addition, the controller supports security extension for implementing a security-aware system.

The PS general interrupt controller (GIC) supports 64 interrupt input lines that are driven from other blocks within the PS or the PL. Six of the 64 interrupt lines are driven from within the APU. These include L1 parity fail, L2 interrupt (all reasons), and PMU (performance monitor unit) interrupt.


The interrupts on the GIC are divided in two three major blocks: Software Generated interrupts (SGIs), Private Peripheral Interrupts (PPIs) and Shared Peripheral Interrupts (SPIs).

Interrupt numbers ID0-ID31 are used for interrupts that are private to a CPU interface and are banked in the distributor. A banked interrupt is one where the distributor can have multiple interrupts with the same ID. A banked interrupt is identified uniquely by its ID number and its associated CPU interface number.

The banked interrupt IDs

• ID0-ID15 SGIs
• ID27-ID31 PPIs

Interrupt numbers from ID32-ID92 are the SPIs to which all the interrupts of the PS-shared peripheral interrupts are connected. From these, 16 of the interrupt sources (ID61 to ID68 and ID84 to ID91) can be driven from the programmable logic.

The GIC collects interrupts from various sources and distributes these interrupts to each of the ARM cores. Each ARM core accepts two different types of interrupts: nFIQ interrupts from secure sources and nIRQ interrupts from either secure or non-secure sources.

The interrupt distributor holds the list of pending interrupts for each Cortex-A9 processor. It selects the highest priority interrupt before issuing it to the Cortex-A9 processor interface. Interrupts of equal priority are resolved by selecting the lowest ID.

The PS to PL and PL to PS interrupts are need to be enabled and mapped to the interrupt lines as per the design requirements. Below figure is an example of PL to PS interrupt configuration in Vivado IPI Zynq block design GIC customization used in this demo:

The prioritization logic is physically duplicated to enable the simultaneous selection of the highest priority interrupt for each Cortex-A9 processor. The interrupt distributor holds the central list of interrupts, processors, and activation information and is responsible for triggering software interrupts to processors. For more details refer the Zynq-7000 AP SoC TRM (UG585).

Reference Design Block Diagram

Figure 3 illustrates the functional blocks of the Zynq-7000 AP SoC interrupt latency measurement hardware design. The PL is instantiated with the six AXI timers, connected to GP0 for the control registers access or programming, the interrupt lines form these timers are connected to:

1. Core 0 FIQ,
2. Core 0 IRQ,
3. Core 1 FIQ,
4. Core 1 IRQ and
5. shared peripheral interrupt line 91.

This design is used to measure the interrupt latency of these all combinations of PL to PS interrupts.

This demo is provided with the reference design. The software implementation is a Linux AMP system where Core 0 will be running Linux and Core 1 will be running the Barem