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ZCU102 Cross Trigger Debug

ZCU102 Cross Trigger Debug


This demos has been created to test Cross Triggering Debug feature, included in the SDK 2016.3 release. Two different use cases are pres
Users are advised to review the Zynq Ultrascale+  Developers Software User guide here

Table of Contents


Build Hardware Platform

Note: The 1.3 version of the zcu102 board files in needed here. These can be downloaded from the headstart lounge prior to completing this demo.
Include a ZYNQ MPSoC device, run default configuration wizard and enable one PL-PS cross triggering port. Also include an ILA IP and configure with the following values.




Include a dummy peripheral in the BD (ie. AXI Timer) and connect the blocks to generate a valid platform design.



Save the project, generate the bitstream and once generated export and launch the SDK.

PL-PS Cross Trigger


This demos is indeed to show how a hardware trigger event can be used to generate a software halt (processor halt) to debug both sides of the device.
Create a peripheral test application for A53 core, and modify the main function (testperiph.c) to include a dummy bus access to the AXI Timer, which is going to be used to trigger the debugger.

Xil_Out32(XPAR_AXI_TIMER_0_BASEADDR, 0xDEADBEEF);



Create a new Debug Configuration
Important: There is a bug in the 2016.3 version of SDK, wherein the zynqmp device is not detected if the debug configuration is not created in the following way