XAPP1078 describes a method of starting up both Zynq Cortex-A9 processors, with CPU0 running Linux, and CPU1 running bare-metal. The included design contains a core that generates interrupts towards CPU1. As CPU1 services the interrupt, it communicates with Linux running on CPU0.
The application note is available on Xilinx's website here: XAPP1078The following list summarizes the additional sections covered on this page:
- Possible Problems Using Git to switch to U-Boot/Linux xilinx-v13-build2 Branch
- Running XAPP1078 on the ZC706 Board
- Running XAPP1078 on the ZedBoard
- Updated Design Files for EDK14.5
- Updated Design Files for Vivado 2014.2 and Petalinux 2014.2 tools
- Updated Design Files for Vivado 2014.4 and Petalinux 2014.4 tools
Possible Problems Using Git to switch to U-Boot or Linux Kernel xilinx-v14.3-build2 Branch
Once the remote repository has been cloned, the now local repository may need to be updated in order to switch to the 'xilinx-v13.3-build2' branch.
Running the following git commands on the cloned repository will update the local repository and checkout the branch.
Running XAPP1078 on the ZC706 Board
In order to run XAPP1078 on the ZC706 board, two modifications need to be made.
- The file cpu1_bootvec.bin needs to be updated to support the WFE loop used to capture CPU1 during boot
- The Linux kernel needs to be configured to send CPU1 back to the WFE loop as the kernel starts
The ROM bootloader in the version 2.0 silicon, used on the ZC706, creates a different WFE loop. In the new loop, once CPU1 is woken up from an interrupt, sev() command or other event, the code will read OCM location 0xFFFFFFF0 and compare the read value to 0xFFFFFF2C. If the value doesn't equal 0xFFFFFF2C, CPU1 will jump to the new value. If the read value is 0xFFFFFF2C, the loop will branch back to the wfe() command.
In XAPP1078, the FSBL completes loading .bin and .elf files once it loads cpu1_bootvec.bin to memory location 0xFFFFFFF0. This file currently contains the value 0xFFFFFF00 which is the starting location of the WFE loop on the ZC702.
Either make the following edits, or download an updated file here:
Using a hex editor, edit work/bootgen/cpu1_bootvec.bin and change its contents from "00 FF FF FF" to "2C FF FF FF".
Once the file is saved (in work/bootgen), re-run 'createBoot.bat' in order to create a new BOOT.BIN file which is then copied to the SD card.
Modifying the Linux Kernel
The Linux kernel contains initialization code for CPU1. This code needs to be modified to send CPU1 back to the WFE loop located at 0xFFFFFF2C.
Edit the file arch/arm/mach-zynq/platsmp.c search for the following line:
and change the line to:
A per-compiled kernel from build 'xilinx-v14.3-build2' with the above change is available here:
Running XAPP1078 on the ZedBoard
The design files have been modified to run on the ZedBoard with the OSL 3.8 kernel from the xilinx-v14.5 tagged repository. The files are available at http://zedboard.org/design
Updated Design Files for EDK14.5
The design files have been updated for EDK14.5. The included U-Boot and Linux Kernel have not changed and still use branch xilinx-v14.3-build2.
The differences between the EDK14.3 and EDK14.5 designs are:
- The linker file for CPU1's application has been updated to work with EDK14.5 BSP
- The standalone BSP, in the repository, has been updated to match standalone_v3_09_a with a few customizations to work with the XAPP
- FSBL now supports multiple ELF files so the customized FSBL has been removed from the repository and the dummy cpu1_bootvec.bin file is no longer required so it has been removed from the bootgen .bif file.
- The XPS project has been rev'd to EDK14.5
Since the FSBL in EDK14.5 supports multiple ELF files, continue following the steps documented in the XAPP but during creation of the FSBL, select the template 'Zynq FSBL'. The 'Zynq FSBL for AMP' template is no longer required and has been removed from the design.
The new design files for EDK14.5 are available here:
The design files have been updated for Vivado 2014.2 and the instructions use Petalinux to build the Linux kernel, ramdisk, etc.
There are scripts and instructions to target the following boards: ZC702 and ZC706. The design includes the source, and generated files that have been tested on ZC702, ZC706, and the Avnet MicroZed boards.
Late breaking updates for early access 2014.2 design:
For ZedBoard(untested)For MicroZed(tested)
When re-opening the design for the microZed board, Vivado may not find the board repository. The fix is to change line 4 of src/scripts/create_proj_microZed.tcl to:
The configuration of the Ethernet phy is missing from the devicetree in the petalinux project for all boards. Before running 'petalinux-build', edit subsystems/linux/configs/device-tree/system-top.dts and add the following to the end of the file:
For ZC706(tested) & ZC702(untested)
The design files have been updated for Vivado 2014.4 and the instructions use Petalinux to build the Linux kernel, ramdisk, etc.There are scripts and instructions to target the following boards: ZC702, ZC706, and the Avnet MicroZed board.
There are also scripts for the Avnet ZedBoard but due to the reduced amount of DDR (512MB), the BSP and cpu1 linkerscript would require modifications. And the Linux kernel bootargs may need the 'mem=' value reduced.
In addition to updating the design to 2014.4, the following additional changes have been made:
- Updated standalone BSP to v4.2 then merged in changes used for 2014.2
- Modified BSP to include capture code for cpu0 and cpu1. This code is not exercised by XAPP1078
- Modified BSP to disable access to DDR between 0x00000000-0x2FFFFFFF
- Modified BSP attributes of DDR address range 0x30000000-0x3FFFFFFF to non-shared and outer cache disabled
- Modified CPU1 app to use the SCU timer instead of global timer via a #define. As long as profiling is not enabled, this change will allow cpu1 to be started either by FSBL or U-Boot.