Table of Contents

Introduction

This page gives an overview of pl330/dmaps DMA driver which is available as part of the Xilinx Vivado and Vitis distribution.

For more information, please refer to PL330 DMA controller chapter in Zynq TRM (UG585).

Driver Sources

The source code for the driver is included with the Vitis Unified Software Platform installation, as well as being available in the Xilinx Github repository. 

The driver source code is organized into different folders.  The table below shows the dmaps driver source organization. 

Note: AMD Xilinx embeddedsw build flow is changed from 2023.2 release to adapt to the new system device tree based flow. For further information, refer to the wiki page Porting embeddedsw components to system device tree (SDT) based flow - Xilinx Wiki - Confluence (atlassian.net).

The .yaml(in data folder) and CMakeLists.txt(in src folder) files are needed for the System Device Tree based flow. The Driver .tcl and .mdd files are for the older build flow which will be deprecated in the future.

Driver Implementation

For a full list of features supported by this IP, please refer to PL330 DMA controller chapter in Zynq TRM (UG585).

Features

Controller/Driver features supported

• Controller supports only Memory to Memory Transfers

• Flexible scatter-gather memory transfers

  • Full control over addressing for source and destination

  • Define AXI transaction attributes

  • Manage byte streams

• Eight cache lines and each cache line is four words wide

• Eight concurrent DMA channels threads

  • Allows multiple threads to execute in parallel

  • Issue commands for up to eight read and up to eight write AXI transactions

• Eight interrupts to the PS interrupt controller and the PL

• Eight events within DMA Engine program code

• 128 (64-bit) word MFIFO to buffer the data that the controller writes or reads during a transfer

• Security

  • Dedicated APB slave interface for secure register accessing

  • Entire controller is configured as either secure or non-secure

• Memory-to-memory DMA transfers

• Four PL peripheral request interfaces to manage flow control to and from the PL logic

  • Each interface accepts up to four active requests

Known Issues and Limitations

• Peripheral interface is not tested/supported

• Unaligned transfers are not supported

Example Applications

DMAPS driver supports a basic interrupt examples describing how its different features can be exercised. These example applications can be imported into the Vitis IDE from the Board Support Package  settings tab. 

Links to Examples

Examples Path:
https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/dmaps/examples

Example Application Usage

DMAPS Interrupt example

Basic DMAPS interrupt example demonstrating one transfer over first channel.

Expected Output

Test round 0
Successfully ran XDMaPs_Example_W_Intr

Example Design Architecture

NA

Performance

NA

Change Log

2024.1

https://github.com/Xilinx/embeddedsw/blob/xilinx_v2024.1/doc/ChangeLog#L868

2023.2

https://github.com/Xilinx/embeddedsw/blob/xlnx_rel_v2023.2/doc/ChangeLog#L554

2023.1

None

2022.2

None

2022.1

None

2021.2

None

2021.1

https://github.com/Xilinx/embeddedsw/blob/xlnx_rel_v2021.1/doc/ChangeLog#L243

2020.2

https://github.com/Xilinx/embeddedsw/blob/release-2020.2/doc/ChangeLog#L612

2020.1

https://github.com/Xilinx/embeddedsw/blob/release-2020.1/doc/ChangeLog#L33

2019.2

https://github.com/Xilinx/embeddedsw/blob/release-2019.2/doc/ChangeLog#L12

2019.1

None

2018.3

None

2018.2

None

2018.1

None

Related Links

• http://www.wiki.xilinx.com/Baremetal+Drivers+and+Libraries