PL330 Standalone Driver


PL330 Standalone Driver


Introduction

This page gives an overview of pl330/dmaps DMA driver which is available as part of the Xilinx Vivado and SDK distribution.

Table of Contents



How to enable

Source path for the driver:
https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/dmaps

Driver source code is organized into different folders. Below diagram shows the dmaps driver source organization

DMAPS
|
-- doc - Provides the API and data structure details
|
- data - Driver tcl and MDD files.
|
- examples - Reference application to show how to use the driver APIs and calling sequence
|
- src - Driver source files

Features Supported

Controller Features

  • Controller supports only Memory to Memory Transfers
  • Flexible scatter-gather memory transfers
    • Full control over addressing for source and destination
    • Define AXI transaction attributes
    • Manage byte streams
  • Eight cache lines and each cache line is four words wide
  • Eight concurrent DMA channels threads
    • Allows multiple threads to execute in parallel
    • Issue commands for up to eight read and up to eight write AXI transactions
  • Eight interrupts to the PS interrupt controller and the PL
  • Eight events within DMA Engine program code
  • 128 (64-bit) word MFIFO to buffer the data that the controller writes or reads during a transfer
  • Security
    • Dedicated APB slave interface for secure register accessing
    • Entire controller is configured as either secure or non-secure
  • Memory-to-memory DMA transfers
  • Four PL peripheral request interfaces to manage flow control to and from the PL logic
    • Each interface accepts up to four active requests

Standalone Driver Supported Features

All Controller Features Supported.

Test cases

---> Refer below pah for testing different examples for each feature of the IP.
https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/dmaps/examples
xdmaps_example_w_intr.c : This is an example which explains how to configure controller feature and how to do
a memory to memory transfer between the Eight concurrent DMA channels.

Known issues and Limitations

  • Peripheral interface is not tested/supported
  • Unaligned transfers are not supported

Change Log

2020.2

Summary:

Support for parallel makefile execution

Commits:

https://github.com/Xilinx/embeddedsw/commits/xilinx-v2020.2/XilinxProcessorIPLib/drivers/dmaps

2020.1

Summary:

Minor bug fix for channel boundary check.

Commits:

https://github.com/Xilinx/embeddedsw/commits/xilinx-v2020.1/XilinxProcessorIPLib/drivers/dmaps

2019.2

Summary:

Minor bug fix adding memory barrier before DMASEV instruction

Commits:

https://github.com/Xilinx/embeddedsw/commits/xilinx-v2019.2/XilinxProcessorIPLib/drivers/dmaps

ea3c8cc dmaps: Add barrier before DMASEV instruction


2019.1

  • None

2018.3

  • None
2018.2
  • None
2018.1
  • None
2017.4
  • None
2017.3
  • None
2017.2
  • None
2017.1
  • None
2016.4
  • None
2016.3
  • None

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