This page gives an overview of the bare-metal driver support for the Xilinx® LogiCORE™ IP AXI Central Direct Memory Access (CDMA) soft IP.

1 Introduction
2 Driver Sources
3 Driver Implementation
- 3.1 Features
- 3.2 Known Issues and Limitations
4 Example Design Architecture
- 4.1 Example Application Usage
  - 4.1.1 Scatter Gather with Interrupts
  - 4.1.2 Scatter Gather with Polling
  - 4.1.3 Simple DMA with Interrupts
  - 4.1.4 Simple DMA with Polling
  - 4.1.5 Hybrid(SG+ simple) with Interrupts
  - 4.1.6 Hybrid(SG+ simple) with Polling
5 Change Log

Introduction

The AXI CMDA core is a soft Xilinx IP core for use with the Xilinx Vivado® Design Suite. The AXI CDMA provides high-bandwidth Direct Memory Access (DMA) between a memory-mapped source address and a memory-mapped destination address using the AXI4 protocol. An optional Scatter Gather (SG) feature can be used to offload control and sequencing tasks from the system CPU. Initialization, status, and control registers are accessed through an AXI4-Lite slave interface. For more information, please refer to the AXI CDMA product page which includes links to the official documentation and resource utilization.

Driver Sources

The source code for the driver is included with the Vitis Unified Software Platform installation, as well as being available in the Xilinx Github repository.

Driver Name	Path in Vitis	Path in Github

Driver Name	Path in Vitis	Path in Github
axicdma	<Vitis Install Directory>/data/embedded/XilinxProcessorIPLib/drivers/axicdma_<version>	https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/axicdma

Note: To view the sources for a particular release, use the rel-version tag in github. For example, for the 2020.1 release, the proper version of the code is: https://github.com/Xilinx/embeddedsw/tree/xilinx-v2020.1/XilinxProcessorIPLib/drivers/axicdma

The driver source code is organized into different folders. The table below shows the axicdma driver source organization.

Directory	Description

Directory	Description
doc	Provides the API and data structure details
data	Driver .tcl, .mdd file and .yaml files
examples	Example applications that show how to use the driver features
src	Driver source files, make and cmake files

Note: AMD Xilinx embeddedsw build flow is changed from 2023.2 release to adapt to the new system device tree based flow. For further information, refer to the wiki page Porting embeddedsw components to system device tree (SDT) based flow - Xilinx Wiki - Confluence (atlassian.net).

The .yaml(in data folder) and CMakeLists.txt(in src folder) files are needed for the System Device Tree based flow. The Driver .tcl and .mdd files are for the older build flow which will be deprecated in the future.

Driver Implementation

For a full list of features supported by this IP, please refer to the AXI CDMA product page.

Features

The AXI CDMA Standalone driver supports the following features:

Supports Simple DMA mode
Supports Scatter/Gather Direct Memory Access (DMA)
Supports 64-bit Addressing
Supports Optional Data Re-Alignment Feature
Supports Register Direct mode

Known Issues and Limitations

All IP features are supported

Example Design Architecture

For simple/SG mode the examples assumes AXI CDMA Data AXI4 Read/Write MasterIP M_AXI/M_AXI_SG interface are connected to DDR.

Example Applications

Refer to the driver examples directory for various example applications that exercise the different features of the driver. Each application is linked in the table below. The following sections describe the usage and expected output of the various applications. These example applications can be imported into the Vitis IDE from the Board Support Package settings tab.

Links to Examples

Examples Path: https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/axicdma/examples

Test Name	Example Source	Description

Test Name	Example Source	Description
Scatter Gather DMA with Interrupts	xaxicdma_example_sg_intr.c	This example demonstrates how to transfer packets in interrupt mode when the core is configured in SG Mode.
Scatter Gather DMA with Polling	xaxicdma_example_sg_poll.c	This example demonstrates how to transfer packets in the polled mode when the core is configured in SG Mode.
Simple DMA with Interrupt	xaxicdma_example_simple_intr.c	This example demonstrates how to transfer packets in interrupt mode when the core is configured in simple DMA Mode.
Simple DMA with Polling	xaxicdma_example_simple_poll.c	This example demonstrates how to transfer packets in the polled mode when the core is configured in simple DMA Mode.
Hybrid(SG+ simple) with Interrupts	xaxicdma_example_hybrid_intr.c	This example demonstrates how to transfer packets in interrupt mode when the core is configured in hybrid(SG + simple) transfer Mode.
Hybrid(SG+ simple) with Polling	xaxicdma_example_hybrid_poll.c	This example demonstrates how to transfer packets in the polled mode when the core is configured in hybrid(SG + simple) transfer Mode.

Example Application Usage

Scatter Gather with Interrupts

This example demonstrates how to transfer packets in interrupt mode when the core is configured in SG Mode.

Expected Output

--- Entering main() ---
Successfully ran XAxiCdma_SgIntr Example
--- Exiting main() ---

Scatter Gather with Polling

This example demonstrates how to transfer packets in the polled mode when the core is configured in SG Mode.

Expected Output

--- Entering main() ---
Successfully ran XAxiCdma_SgPoll Example
--- Exiting main() ---

Simple DMA with Interrupts

This example demonstrates how to transfer packets in interrupt mode when the core is configured in simple DMA Mode.

Expected Output

--- Entering main() ---
Successfully ran XAxiCdma_SimpleIntr Example
--- Exiting main() ---

Simple DMA with Polling

This example demonstrates how to transfer packets in the polled mode when the core is configured in simple DMA Mode.

Expected Output

--- Entering main() ---
Successfully ran AxiCdma_SimplePoll Example
--- Exiting main() ---

Hybrid(SG+ simple) with Interrupts

This example demonstrates how to transfer packets in interrupt mode when the core is configured in hybrid(SG + simple) transfer Mode.

Expected Output

--- Entering main() ---
First simple transfer successful
Scatter gather transfer successful
Second simple transfer successful
Successfully ran Axicdma Hybrid interrupt Example
--- Exiting main()

Hybrid(SG+ simple) with Polling

This example demonstrates how to transfer packets in the polled mode when the core is configured in hybrid(SG + simple) transfer Mode.

Expected Output

--- Entering main() ---
First simple transfer successful
Scatter gather transfer successful
Second simple transfer successful
Successfully ran Axicdma Hybrid polled Example
--- Exiting main()