Common Clock Framework for Zynq

Owned by shubhro (Unlicensed)
Last updated: Nov 13, 2024 by Datta, Shubhrajyoti

This page gives an overview of the Zynq Clock framework available at drivers/clk/zynq/. 


Table of Contents


HW IP features


The Zynq has a programmable clock generator that takes a clock of a definite input frequency and generates multiple derived clocks using the phase-locked loop (PLL) blocks in the processing system (PS). The output clock from each of the PLLs is used as a reference clock to the different PS peripherals. Clocking Features The Zynq UltraScale+ MPSoC has five PLLs that generate various clocks used in the PS subsystem:

Features Supported in the Driver


  • Clock gating
  • Clock scaling

Missing features, Known Issues, limitations

  • NA

Kernel Configuration

The following config options should be enabled in order to build the ccf driver

Compiled default.

Devicetree 

For more details on phy bindings please refer "Documentation/devicetree/bindings/clock/zynq-7000.txt"

clkc: clkc@100 {
                                u-boot,dm-pre-reloc;
                                #clock-cells = <1>;
                                compatible = "xlnx,ps7-clkc";
                                fclk-enable = <0xf>;
                                clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
                                                "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
                                                "dci", "lqspi", "smc", "pcap", "gem0", "gem1",
                                                "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
                                                "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
                                                "dma", "usb0_aper", "usb1_aper", "gem0_aper",
                                                "gem1_aper", "sdio0_aper", "sdio1_aper",
                                                "spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
                                                "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
                                                "gpio_aper", "lqspi_aper", "smc_aper", "swdt",
                                                "dbg_trc", "dbg_apb";
                                reg = <0x100 0x100>;
                        };

Test Procedure


Mainly clock enable and disable based on a usage basis.


Upon the usage the the clocks are enabled and in the idle the clocks are gated.

Mainline status
Mainlined

Change log

2024.2

None

2024.1

None

2023.2

None

Related Links

© Copyright 2019 - 2022 Xilinx Inc. Privacy Policy