Zynq Pl353 SMC and NAND drivers

Introduction

This documents provides the details about the Pl35x smc and pl35x nand drivers located in drivers/memory/pl353-smc.c and drivers/mtd/nand/raw/pl353_nand.c
Link for the source files: pl353-smc.c and pl353_nand.c

The SMC (PL353) supports two memory interfaces:
  • Interface 0 type SRAM/NOR.
  • Interface 1 type NAND.

For NOR, it is generic Linux CFI driver.

HW/IP Features

Controller Features

  • ONFI 1.0 compatible
  • supports up to 1GB device
  • 8/16-bit IO width with a single chip select
  • 16-word read/write FIFOs
  • 8-word command FIFO
  • Programmable IO Cycle timing
  • 1-bit ECC hardware with sw assist
  • Asynchronous memory operating mode

Driver Features

  • Supports only the mandatory ONFI 1.0 commands. i.e Reset, Read status, Read ID, Read Parameter Page, Read Page, Program Page, Erase Block, Set/Get Features
  • Supports BBT management
  • Supports ondie ecc devices
  • Support for hw ecc and sw ecc
  • support for 8 and 16 bit flash devices
  • Support for configuring the nand and nor timing parameters

Missing Features, Known issues, limitations

  • HW ecc support for devices with 2K page size up and oobsize up to 64 bytes. Beyond that the driver will choose sw ecc mechanism.
  • Driver has auto detection mechanism for ondie ecc devices and this support is available only for micron devices with oob size 64 bytes
  • NOR driver has been tested for single chip select configuration

Bad Block management

As part of the bbt management, driver reserves the last 4 blocks of the flash device for storing the bbt information. bbt management is similar to the standard Linux algorithm except the offset of storing the BBT signature and version; and also the locations reserved for storing the ecc information.

Kernel Configuration options

SMC Driver

The following kernel configuration options should be enabled for compiling the pl353 smc driver

Device Drivers -> Memory Control Drivers -> ARM PL353 Static Memory Controller(SMC) driver

CONFIG_ARM = y
CONFIG_PL353_SMC = y



NAND Driver

The following kernel configuration options should be enabled for compiling the pl353 smc nand driver

Device Drivers -> Memory Technology Device (MTD) support -> NAND Device Support ->ARM PL353 NAND flash driver

CONFIG_MTD_NAND = y
CONFIG_ARM = y
CONFIG_PL353_SMC = y
CONFIG_MTD_NAND_PL35X = y



NOR Driver

Select the Device Drivers option and then, select Memory Technology Devices (MTD).
Finally, choose the RAM/ROM/Flash chip drivers option.
Detect flash chips by common flash interface (CFI) by selecting one of the following:
  • For the static build, choose the option <*> Detect flash chips by Common Flash Interface (CFI).
  • For build as a module, choose the option <M> Detect flash chips by Common Flash Interface (CFI).
To build support for the AMD select one of the following:
  • For static build, choose the option <*> Support for AMD/Fujitsu flash chips.
  • For build as a module, choose the option <M> Support for AMD/Fujitsu flash chips.
To build support for Intel select one of the following:
  • For static build, choose the option <*> Support for Intel/Sharp flash chips.
  • For build as a module, choose the option <M> Support for Intel/Sharp flash chips.
To build support for Mapping drivers for chip access
  • For static build, <*> Flash device in physical memory map based on OF description
  • For build as a module, <M> Flash device in physical memory map based on OF description



Device Tree

For more details on nand devicetree details, please refer Documentation/devicetree/bindings/mtd/nand.txt
Link: Device Tree Binding info

The timing parameters t0, t1, t2, t3, t4, t5, t6 denotes
nand-cycle-t0 : Read cycle time(t_rc).
nand-cycle-t1 : Write cycle time(t_wc).
nand-cycle-t2 : re_n assertion delay(t_rea).
nand-cycle-t3 : we_n de-assertion delay(t_wp).
nand-cycle-t4 : Status read time(t_clr)
nand-cycle-t5 : ID read time(t_ar)
nand-cycle-t6 : busy to re_n(t_rr)

Performance

ModeWrite SpeedRead Speed
8 bit8MB/sec9.5MB/sec
16bit  7MB/sec 11.1MB/sec


Test Procedure


JFFS2 filesystem


How to Run

UBIFS file system







Images:

Flashcp


mtd_speedtest


Select the mtd_speedtest from the kernel configuration menu:



Build it as module and use the generated .ko from the location drivers/mtd/tests/

How to run

Speed Test

Expected Output



oob test


Expected Output


Change Log

  • 2016.3

    • Summary
      • None
    • Commits
      • None
  • 2016.4

    • Summary
      • None
    • Commits
      • None
  • 2017.1

    • Summary
      • Update smc nand driver as per latest kernel changes
    • Commits
  • 2017.2

    • Summary
      • None
    • Commits
      • None
  • 2017.3

    • Summary
      • None
    • Commits
      • None
  • 2017.4

    • None
  • 2018.1

    • Summary
      • Do bit operations on offset not on virtual address
    • Commits
  • 2018.2

    • Summary
      • Fix for incorrect ooblayout offset update
    • Commits
  • 2018.3

    • Summary
      • Implement De-select in chip select
      • Add ECC checking for on-die nand flash
    • Commits
  • 2019.1

    • Summary
      • Implemented →exec_op
    • Commits
  • 2019.2

    • Summary
      • None
    • Commits
      • None
  • 2020.1

    • Summary
      • Updated the driver as per new kernel NAND framework
    • Commits
      • 75721e47 updated the driver under new NAND framework
  • 2020.2

    • Summary
      • Removed unused variable
      • Initialized variable before using it
      • Fixed incompatible assignment
    • Commits

Mainline Status

PL353 SMC Driver - Done