Linux Trafficgen Driver

Introduction

This information corresponds to the Traffic generator driver is available at drivers/misc/xilinx_trafgen.c
This driver supports the axi traffic generator IP.

H/W or IP features

AXI4 interface for register access and data transfers.

• Flexible data width capability (32/64-bit) on output AXI4-memory map Slave, (32/64/
128/256/512-bit) on output AXI4-memory map Master interface
• Flexible data width capability from 8-bit to 1,024-bit in multiples of eight output
AXI4-stream Master/Slave interface
• Interrupt support for indicating completion for traffic generation.
• Error interrupt pin indicating error occurred during core operation. Error registers can
be read to understand the error occurred.

Only supported in Advanced mode.

• Initialization support through Memory initialization files to internal RAM (CMDRAM, PARAMRAM, and MSTRAM)
allows you to initialize the contents of all RAMs for a desired traffic profile.


Features Supported in driver


• Flexible data width capability (32/64-bit) on output AXI4-memory map Slave, (32/64/
128/256/512-bit) on output AXI4-memory map Master interface
• Flexible data width capability from 8-bit to 1,024-bit in multiples of eight output
AXI4-stream Master/Slave interface
• Interrupt support for indicating completion for traffic generation.
• Error interrupt pin indicating error occurred during core operation. Error registers can
be read to understand the error occurred.

Only supported in Advanced mode.

• Initialization support through Memory initialization files to internal RAM (CMDRAM, PARAMRAM, and MSTRAM)
allows you to initialize the contents of all RAMs for a desired traffic profile.

Missing Features and known Issues/Limitations in Driver

None

Kernel Configuration

Xilinx Trafgen driver is not enabled in the current default kernel configuration. The following steps may be used to enable the driver in the kernel configuration

Devicetree
For More details about the device-tree bindings please refer to the Documentation/devicetree/bindings/misc/xilinx-axitrafgen.txt file.


Test Procedure

Application for Advanced Mode or Basic Mode:

The application demonstrates by programming known data to Master RAM and commands to Command RAM. Initiating the master logic will take the data from Master RAM (from a location) and generate data for slave transactions which is directed to write into BRAM. And then write commands in Command RAM read the data from BRAM and write it back to Master RAM at a different location. The test passes when the master logic completes and verifies for data to same.
This example does mmap to Master RAM:

atg_test.c
Note:

This example is based on h/w design with traffic generator connected to cores BRAM and DDR via an interconnect. This example tests the IP using BRAM, alternatively, you can use the DDR address map. If you are using DDR addresses ensure the address range is unmapped to the kernel.Also, modify the defines(PRAM_SYS_PATH, CRAM_SYS_PATH, MRAM_SYS_PATH, LAST_VALID_INDEX_PATH, START_MASTER_PATH, AXI_ADDRESS) in the examples according to your design.



Alternatlvely user can create bin files of their respective sizes (Master RAM -8K size) and then write directly to Master RAM from the linux prompt,
Bin files can be easily created using open source 'hexedit' tool. An example usage case is provided below to test RAMs.
$LINUX > cat 8K.bin > /sys/devices/axi.0/44a00000.axi-traffic-gen/driver/master_ram
/* Write to Master RAM */
$LINUX > cat /sys/devices/axi.0/trafgen0/44a00000.axi-traffic-gen/driver/master_ram > sri.bin /* Read from Master RAM */
$LINUX > diff 8K.bin sri.bin /* Compare both data */
$LINUX > hexdump -v -C sri.bin > temp.bin /* To see the contents of bin file */
BIN File:


NOTE: This example is based on h/w design with traffic generator connectedto cores BRAM and DDR via an interconnect. This example tests the IP using BRAM, alternatively you can use DDR address map. If you are using DDR addresses ensure the address range is unmapped to kernel.


Application for Streaming Mode:

This application demonstrates how to use the Streaming mode in the Axi traffic generator .In the Streaming mode the core generates Streaming traffic based

on the transfer length and transfer count configured.

Application:



NOTE: This example is based on h/w design with traffic generator connected to the axi Stream fifo.


Application for Static Mode:

This application demonstrates how to use the Static mode in the Axi traffic generator In static mode the core continuously generates fixed address and
fixed INCR type read and write transfers based on the burst length configured.
This example does mmap to the Bram memory inorder check the static mode

Application:



NOTE: This example is based on h/w design with traffic generator connected to cores BRAM and DDR via an interconnect. This example tests the IP using BRAM, alternatively you can use DDR address map. If you are using DDR addresses ensure the address range is unmapped to kernel.

Mainline Status

Not mainlined

Change Log
  • 2016.3
    • None
  • 2016.4
    • None
  • 2017.1
    • None
  • 2017.2
    • None
  • 2017.3
Summary:
  • Fix the clearing of ram
  • Warning Fixes
Commits:
misc: trafgen: Fix the clearing of ram
misc: xilinx_trafgen: Fix warnings in the driver

  • 2017.4
Summary:
  • Fix the extended ram offset
Commits:
misc: atg: Fix the offset for the extended command ram
  • 2018.1
    • None
  • 2018.2
    • None
  • 2018.3
Summary:
  • misc: xilinx_trafgen: Add clock support
  • misc: xilinx_trafgen: Add loop enable support 
  • misc: xilinx_trafgen: Fix teh last_valid_index
Commits:
misc: xilinx_trafgen: Add clock support
  • 2019.1
Summary:
  • misc: xilinx_trafgen: Update the sysfs entries
Commits:
misc: xilinx_trafgen: Update the sysfs entries
  • 2019.2
Summary:
  • misc: xilinx_trafgen: Add stream config support
Commits:
misc: xilinx_trafgen: Add stream config support
  • 2020.1 

Summary:

  • misc: trafgen: Fix coding style

Commits:
misc: trafgen: Fix coding style

  • 2020.2

Summary:

  • misc: trafgen: fix out of scope warning

Commits:
misc: trafgen: fix out of scope warning

  • 2021.1
    • None