Introduction

The Xilinx analog mixed signal module, referred to as the XADC, is a hard macro. It has JTAG and DRP interfaces for accessing the XADC’s status and control registers in the 7-series FPGAs.
Zynq-7000 AP SoC devices add a third interface, the PS-XADC interface for the PS software to control the XADC. The Zynq-7000 AP SoC devices combine a flexible analog-to-digital converter with programmable logic to address a broad range of analog data acquisition and monitoring requirements. The XADC is part of a larger analog mixed signal (AMS) topic that is a combination of analog and digital circuits.

HW/IP features

Analog-to-Digital Converters

Dual 12-bit 1 MSPS analog-to-digital converters (ADCs)
Up to 17 flexible and user-configurable analog inputs
On-chip or external reference option
On-chip temperature and power supply sensors
JTAG access to ADC measurements

PS-XADC Interface

Read and write XADC registers
Serial data transfers to/from XADC
Buffered read-write data operations
15-word by 32-bit command FIFO
15-word by 32-bit
Read Data FIFO
Programmable FIFO-level interrupts
Programmable alarm interrupts
Configured interface operations (using devcfg registers)
DRP Parallel Interface
Highest interface bandwidth
6-bit sample data

PL-JTAG Interface

Access the XADC when the PL is not programmed but is powered-up
Uses the JTAG TAP controller to access the XADC registers

Missing features, Known Issues, limitations

System Monitor/ADC device can be accessed through the JTAG port and AXI interface. The driver implementation does not support the simultaneous access of the device by both these interfaces. The user has to care of this situation in the user application code.

Kernel configurations

To compile a kernel with a driver for the XADC enable the following kernel config option:

CONFIG_XILINX_XADC

Device Tree Settings

xadc@f8007100 {
        compatible = "xlnx,zynq-xadc-1.00.a";
        reg = <0xf8007100 0x20>;
        interrupts = <0 7 4>;
        interrupt-parent = <&gic>;
        clocks = <&pcap_clk>;
 
        xlnx,channels {
            #address-cells = <1>;
            #size-cells = <0>;
            channel@0 {
                reg = <0>;
            };
            channel@1 {
                reg = <1>;
            };
            channel@