Intc
Introduction
This page gives an overview of intc driver which is available as part of the Xilinx Vivado and Linux distribution.
The LogiCORE™ IP AXI Interrupt Controller (INTC) core receives multiple interrupt inputs from peripheral devices and merges them into an interrupt output to the system processor. The registers used for storing interrupt vector addresses, checking, enabling and acknowledging interrupts are accessed through the AXI4-Lite interface.
HW/IP Features
Support up to 32 interrupt inputs
Capable of cascading
Enabling and disabling of individual interrupts.
Capable of generating software interrupts
Features supported in driver
Single AXI INTC IP supports 32 interrupts, multiple AXI INTC IP's can be cascaded, to support more than 32 interrupt inputs
Supports chaining with GIC "PL peripheral→ AXI INTC→ GIC→ ARM processor"
Experimental support to load driver as module (IRQCHIP Xilinx Intc driver module support)
Enable that feature in the kernel configuration when using the AXI INTC in a PL overlay
Devicetree
axi_intc_1: interrupt-controller@41200000 {
#interrupt-cells = <2>;
compatible = "xlnx,xps-intc-1.00.a";
interrupt-controller ;
reg = <0x41200000 0x10000>;
xlnx,kind-of-intr = <0x1>;
xlnx,num-intr-inputs = <0x3>;
};
Mainline status
Existing driver https://github.com/Xilinx/linux-xlnx/blob/master/drivers/irqchip/irq-xilinx-intc.c is in sync with mainline driver except following features,
Microblaze SMP support related changes in driver
Experimental support to load driver as module, kconfig IRQCHIP_XILINX_INTC_MODULE_SUPPORT_EXPERIMENTAL has to be enabled to use this feature
Boot log snippets
NR_IRQS:33
/amba_pl/interrupt-controller@41200000: num_irq=3, edge=0x1
Changelog
2024.2
f513e91 ("irqchip: xilinx: adopt clock support")
2024.1
v6.6 Kernel rebase
2023.2
None
2023.1
None
2022.2
None
2022.1
v5.15 Kernel rebase
2021.2
None
2021.1
Added experimental support to load driver as module.
Related Links
AXI Interrupt Controller (INTC) v4.1 Product Guide
Cascade Interrupt Controller support in DTG
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