Xilinx Phy VideoPhy Driver
Table of Contents
Introduction
The Xilinx® Video PHY Controller LogiCORE™ IP core is designed for enabling plug-and-play connectivity with Video (DisplayPort and HDMI® technology) MAC Transmit or Receive subsystems.
The interface between the video MAC and PHY layers are standardized to enable ease of use in accessing shared transceiver resources. The AXI4-Lite register interface is provided to enable dynamic accesses of transceiver controls/status
Video IP Layer
Driver Overview
The PHY is intended to simplify the use of serial transceivers and adds domain-specific configurability. The Video PHY Controller IP/Driver is not intended to be used as a stand alone IP and must be used with Xilinx Video MACs such as HDMI 1.4/2.0 Transmitter/Receiver Subsystems and DisplayPort TX/RX Subsystems.
As such PHY Linux Driver is implemented within the kernel PHY framework and is tightly coupled with HDMI Rx/Tx and DP Rx/Tx Linux drivers. This driver also hosts the common video files shared between the 3 Xilinx connectivity drivers (Vphy, HDMI Rx, HDMI Tx, DP Rx and DP Tx) and exports the relevant API’s for inter-driver communication. On kernel boot-up both HDMI Rx/Tx & DP Rx/Tx drivers will request 3 PHY lanes each for Rx & Tx and will defer until PHY driver has been initialized.
IP/Driver Features
IP Feature | 2018.1 - 2019.1 | 2019.2 and onward | 2023.2 and onward |
compatible string for versal | xlnx,hdmi-gt-controller-1.0 | xlnx,hdmi-gt-controller-1.0 | xlnx,hdmi-gt-controller-1.0 |
compatible string for ZynqMP | xlnx,vid-phy-controller-2.2 | xlnx,vid-phy-controller-2.2 | xlnx,vid-phy-controller-2.2 |
IP Version Supported | 2.2 | 2.2 | 2.2 |
AXI4-Lite support for register accesses | Y | Y | Y |
Protocol Support: Display Port, HDMI | Only HDMI | Only HDMI | DisplayPort and HDMI |
Full transceiver dynamic reconfiguration port (DRP) accesses and transceiver functions | Y | Y | Y |
Independent TX and RX path line rates (device specific) | Y | Y | Y |
Single quad support | Y | Y | Y |
Phase-locked loop (PLL) switching support from software | Y | Y | Y |
Transmit and Receiver user clocking | Y | Y | Y |
Protocol specific functions (For example, HDMI Clock Detector) | Y | Y | Y |
Non-integer data recovery unit (NI-DRU) support for lower line rates. NI-DRU support is for the HDMI protocol only. | Y | Y | Y |
Advanced Clocking Support | N | N | Y |
Use of 4th GT channel as TX TMDS clock | N | Y | Y |
HW IP Configuration
VPHY IP configuration for HDMI:
VPHY IP configuration for DisplayPort:
Known Issues and Limitations
Only 1 IP configuration supported (listed in HW IP Configuration section)
Kernel Configuration Options for Driver
2018.1 and onwards: CONFIG_ARCH_ZYNQMP and CONFIG_GENERIC_PHY should be enabled
Driver is added as an out-of-tree kernel module and therefore requires no driver specific kernel configuration However to enable the driver user must include it in the rootfs. Following steps are required enable the driver
Make sure the meta-user layer has the recipe-hdmi or recipe-dp included
For 2019.2 onwards
Add the recipe to petalinux image. Edit ./meta-user/conf/user-rootfsconfig and add the new recipe at the end
CONFIG_kernel-module-hdmior
CONFIG_kernel-module-dpFor 2018.1 to 2019.1
Add the recipe to petalinux image. Edit ./meta-user/recipes-core/images/petalinux-image-full.bbappend and add the new recipe at the end
NOTE - While using 2018.1 petalinux, the file name was ./meta-user/recipes-core/images/petalinux-image.bbappend
IMAGE_INSTALL_append = " kernel-module-hdmi"or
IMAGE_INSTALL_append = " kernel-module-dp"Next include the driver in the rootfs
% petalinux-config -c rootfsSelect "user-pakages->modules->kernel-module-hdmi", save and exit or
Select "user-pakages->modules->kernel-module-dp", save and exit
Build the project
%petalinux-buildDevice Tree Binding
The dts node should be defined with correct hardware configuration. How to define the node is documented in
2025.2:Documentation/devicetree/bindings/xlnx,vphy.txt
2025.1 Documentation/devicetree/bindings/xlnx,vphy.txt
2021.2: Documentation/devicetree/bindings/xlnx,vphy.txt
2021.1: Documentation/devicetree/bindings/xlnx,vphy.txt
2020.2: Documentation/devicetree/bindings/xlnx,vphy.txt
2020.1: Documentation/devicetree/bindings/xlnx,vphy.txt
2019.2: Documentation/devicetree/bindings/xlnx,vphy.txt
2019.1: Documentation/devicetree/bindings/xlnx,vphy.txt
2018.3: Documentation/devicetree/bindings/xlnx,vphy.txt
2018.1: Documentation/devicetree/bindings/xlnx,vphy.txt
DEBUG Capability
Video PHY Linux driver implements the capability to tap IP status at pre-defined points in the control flow. User can enable the debug taps by uncommenting the pre-processor directive (#define DEBUG) to monitor the progress within the driver. All debug prints are sent to serial console and can be viewed in kernel dmesg buffer
How to capture vphy state machine logs
Run below command to print the vphy state machine logs or vphy information
# For Logs, run anyone of the below. It will give logs for both TX and RX state machine logs of vphy. Do note that its a destructive logging. Once you run below command, the logs buffer will become empty.
cat /sys/devices/platform/amba_pl\@0/80080000.v_hdmi_tx_ss/vphy_info
or
cat /sys/devices/platform/amba_pl\@0/80000000.v_hdmi_rx_ss/vphy_log
# For vphy info, run below commands
cat /sys/devices/platform/amba_pl\@0/80080000.v_hdmi_tx_ss/vphy_log
or
cat /sys/devices/platform/amba_pl\@0/80000000.v_hdmi_rx_ss/vphy_infoHow to capture register dump
Create a script on target and name it as dumpmem.sh. Paste below content in that script.
#!/bin/sh
# Usage dumpmem.sh ADDR OFFSET
base=$1
counter=0
while [ $counter -lt $2 ];
do
offset=$(($counter*4))
reg_addr=$(($base + $offset))
reg_addr=`printf "0x%X\n" $reg_addr`
output=$(devmem $reg_addr)
delimiter=": "
echo $reg_addr$delimiter$output
counter=$(($counter+1))
done
echo All doneNow run below command to dump the registers of Vphy
# In the below command, first parameter is the base address of the IP (vphy) in this case and second parameter is the number of registers to be read
./dumpmem.sh 0x80120000 206Boards Supported
Driver has been tested on following boards
zcu102 Rev 1.0
Zcu106 Rev 1.0
Driver has been tested with HDMI FrameBuffer Example Design design
Change Log
2025.2
Summary:
2025.1
Summary:
2024.2
2024.1
2023.2
Commits
2023.1
2022.2
2022.1
Commits
2021.2
Commits
2021.1
Summary
Update the phy driver based on bare metal driver updates to components like hdcp, video common library, etc.
Commits
2020.2
Summary
Fix coverity warnings
Remove GT workaround patch
Add helpers to parse and generate HDR Aux packets
Commits
2020.1
Summary
Add support for Versal Phy (HDMI GT controller) in same driver
Add minor fixes and updates
Fix sha
Add VIC entries
memset packet structure to 0 while generating
Commits
2019.2
Summary
Driver updated for 2019.2
Enabled TX 4th GT channel support
Enabled suspend and resume
Updated license file for 2019.2
Commits
2019.1
Summary
Made driver compliant with DTG tool generated Device tree nodes and updated the documentation.
Updated license file for 2019.1
Commits
2018.3
Summary
Made dru clock optional depending on NI-DRU configured value
Commits
2018.1
Summary
Added 0.5% margin to user clock frequency
Commits
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