Cadence I2C Driver

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Introduction

This page provides information about the Cadence I2C driver which can be found on Xilinx Git and mainline as i2c-cadence.c
Zynq has two I2C hard IP. I2C can be used as a master with this linux driver.
There is support for repeated start with some limitations.

HW IP Features

  • Master mode
  • Support 16 bytes FIFO
  • Programmable normal and fast bus data rates
  • Interrupt support
  • Repeated start support using HOLD bit
  • FIFO control using HOLD bit
  • Slave monitoring support in Master mode.


Known issues and limitations

  • Repeated start after a read transfer is not supported by this controller. A warning is given when this condition is detected by the driver.
  • The following are the controller errata:
  • Missing glitch filter.
  • I2C Master Generates Invalid Read Transactions
  • Missing I2C Master Completion Interrupt.
  • Timing requirement violations
    • I2C - Standard Mode running faster than 90 kHz violates tHD; STA timing requirement.
    • I2C - Fast Mode running faster than 384kHz violates tLOW; STA timing requirement.
    • I2C - Fast Mode running faster than 384 kHz violates tBUF; STA timing requirement.
  • I2C Missing Arbitration On Repeated Start.

Important AR links

  • Zynq-7000 AP SoC, I2C - Missing Glitch Filter Implementation in Zynq PS I2C Controller AR# 61861
  • Zynq-7000 AP SoC, I2C - I2C Master Generates Invalid Read Transactions AR# 61664
  • Zynq-7000 AP SoC, I2C - Missing I2C Master Completion Interrupt AR# 61665
  • Zynq-7000 AP SoC, I2C - I2C Missing Arbitration on Repeated Start AR# 60695
  • Zynq-7000 AP SoC, I2C - Standard Mode running faster than 90 kHz violates tHD; STA timing requirement AR# 59366
  • Zynq-7000 AP SoC, I2C - Fast Mode running faster than 384kHz violates tLOW; STA timing requirement AR# 60693
  • Zynq-7000 AP SoC, I2C - Fast Mode running faster than 384 kHz violates tBUF; STA timing requirement AR# 60694

Kernel Configuration

The following config options need to be enabled:
CONFIG_I2C_CADENCE

It depends on I2C and ARCH_ZYNQ



Devicetree

Refer to Documentation/devicetree/bindings/i2c/i2c-cadence.txt for complete description.
Example
The following example shows adding an I2C node to the devicetree with the various interfaces connected to i2c on zynq zc702 board:

Test procedure


This section details i2c tests with various interfaces:
Eeprom Test helper script
Writes different patterns to the I2C EEPROM, reads back the contents of the EEPROM and performs data verification.
Inputs expected by the helper script (i2c_eeprom_helper.sh), in that order:
1. The EEPROM to test in the /sys filesystem, a full path
2. Offset from the start of the EEPROM
3. The number of bytes to read/write at the offset from the start of the EEPROM.

I2C eeprom helper script & test logs:



EEPROM Stress Test
The following test can be used for performing eeprom stress test:


Testing RTC
Read Date and Time from RTC

Testing UCD9248
TI's UCD9248 PWM controllers are commonly used on Xilinx platforms like the zc702.
The Linux driver for these controllers allows voltage and current monitoring through a sysfs interface exposed in /sys/bus/i2c/devices/*.
The driver is documented in Documentation/hwmon/ucd9200

Testing I2C EEPROM
Basic test on zynq zc702 board:
1. Create BIN file using DD command

2. Write BIN file to EEPROM

3. Read Data From EEPROM

Expected Output

Verify data using md5sum tools

Mainline Status

This driver is currently in sync with mainline kernel except for the following:

Bug fixes (1), Slave monitor mode feature (1), Recover bus feature (2), Coverity fixes (2) as detailed below:

  • i2c: cadence: Clear HOLD bit before xfer_size register rolls over
  • i2c-cadence: Replace the value with enum
  • i2c-cadence: Check the return value of pin-ctrl
  • i2c: cadence: Handling Slave monitor mode
  • i2c: cadence: Recover bus after controller reset
  • i2c: cadence: Implement save restore


ChangeLog


  • 2016.3
    • None
  • 2016.4
    • None
  • 2017.1
    • Summary
      • i2c: cadence: Recover bus after controller reset
      • i2c: cadence: Fix pin controller failure
      • I2c: Fix the i2c Bus Recovery issue.
      • i2c: cadence: Added slave support
      • i2c: cadence: Fix wording in i2c-cadence driver

  • Commits
    • 0b4e260 i2c: cadence: Recover bus after controller reset
    • b6811d3 i2c: cadence: Fix pin controller failure
    • 5639be4 I2c: Fix the i2c Bus Recovery issue.
    • f2290d9 i2c: cadence: Added slave support
    • 2c3fd0a i2c: cadence: Fix wording in i2c-cadence driver

  • 2017.2
    • None
  • 2017.3
    • Summary
      • i2c: Re-order the interrupt enable sequence in the i2c send and receive path
      • i2c: cadence: Fixed repeated start not holding the bus long enough
      • i2c: cadence: Remove pm_runtime_disable
    • Commits
      • 1692844 i2c: Re-order the interrupt enable sequence in the i2c send and receive path
      • 9e90cc1 i2c: cadence: Fixed repeated start not holding the bus long enough
      • 4293372 i2c: cadence: Remove pm_runtime_disable
  • 2017.4
    • None
  • 2018.1
    • Summary
      • i2c: use dev_get_drvdata() to get private data in suspend/resume hooks
      • i2c: cadence: Fixed repeated start not holding the bus long enough
    • Commits
      • 9242e72 i2c: use dev_get_drvdata() to get private data in suspend/resume hooks
      • 9e90cc1 i2c: cadence: Fixed repeated start not holding the bus long enough
  • 2018.2
    • None


  • 2018.3
    • None


Related Links
None