Xilinx GMII2RGMII converter
Table of Contents
Introduction
This page describes the Xilinx GMII2RGMII converter IP which can be found at /drivers/net/phy/xilinx_gmii2rgmii.c
This converter can be used with any MAC device, either axi ethernet or Zynq/Zynq Ultrascale+ MPSoC GEM.
Paths, files, links and documentation on this page are given relative to the Linux kernel source tree.
HW IP features
GMII2RGMII conversion
Features supported in driver
GMII2RGMII conversion
Missing Features, Known Issues and Limitations
None
Kernel Configuration
XILINX_GMII2RGMII
Devicetree
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy: ethernet-phy@0 {
......
};
gmiitorgmii: gmiitorgmii@8 {
compatible = "xlnx,gmii-to-rgmii-1.0";
reg = <8>;
phy-handle = <&phy>;
clocks = <&fixedplaceholder>;
clock-names = "clkin";
};
};The clocks and clock-names properties are not automatically generated. Users must manually define and update these properties based on their design.
Complete devicetree documentation can be found here: https://github.com/Xilinx/linux-xlnx/blob/master/Documentation/devicetree/bindings/net/xlnx%2Cgmii-to-rgmii.yaml
Test Procedure
This phy can be tested with any MAC using general ethernet test procedures like ping, iperf/netperf.
Refer to http://www.wiki.xilinx.com/Macb+Driver#Test Procedure
Mainline status
This driver is currently in sync with mainline except for the following diff:
Clock adaption support (accepted on mainline net-next, expected to be in sync by 6.11)
Change Log
2025.1
No changes
2024.2
No changes
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