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AMD TSN Solution

AMD TSN Solution

Time-Sensitive Networking (TSN) is a set of standards under development by the Time-Sensitive Networking task group of the IEEE 802.1 working group.

Information is provided here, on the Software TSN Solution for FPGA based TSN subsystem (https://www.xilinx.com/products/intellectual-property/1gtsn.html)

 

Table of Contents

HW Features of Soft IP based 100M/1G TSN Subsystem

  • Enhanced Time Synchronization using IEEE 802.1AS

  • Ethernet AVB (Audio Video Bridging, IEEE 802.1Qav)

  • Frame Replication and Elimination for Reliability IEEE 802.1CB

  • Enhancements for Scheduled Traffic IEEE 802.1Qbv

  • Per-Stream Filtering and Policing, IEEE 802.1 Qci

  • Enhancements and Performance Improvements, IEEE 802.1Qcc

  • Frame Preemption, IEEE 802.1Qbu

  • Interspersing Express Traffic, IEEE 802.3br



Software support

Soft IP TSN kernel drivers are currently supported in Xilinx Linux staging area: linux-xlnx/drivers/staging/xilinx-tsn at master · Xilinx/linux-xlnx

Soft IP TSN user space utilities and sample configurations are provided to enable TSN functionality. Please refer to the TSN SW user guide and the following sections for more details.

TSN application are available via utilities and examples here (can be built via AMD Yocto recipes):

https://github.com/Xilinx/tsn-utils

https://github.com/Xilinx/tsn-talker-listener

To include the above applications in the root filesystem, please follow the steps below

Yocto:
Enable tsn packages using below line in local.conf
IMAGE_INSTALL:append = "packagegroup-tsn"

Note: Make sure you have included meta-xilinx-tsn layer in bblayers.conf

Petalinux:
For petalinux, update petalinuxbsp.conf with below line
IMAGE_INSTALL:append = "packagegroup-tsn"

To compile applications in the PetaLinux flow, please refer to the following links:
AMD Technical Information Portal
AMD Technical Information Portal

Kernel Configuration

The following config options should be enabled in order to build the TSN Subsystem:

CONFIG_XILINX_TSN

CONFIG_AXIENET_HAS_TADMA

CONFIG_XILINX_TSN_PTP

CONFIG_XILINX_TSN_QBV

CONFIG_XILINX_TSN_SWITCH

CONFIG_XILINX_TSN_QCI

CONFIG_XILINX_TSN_CB

CONFIG_XILINX_TSN_QBR



The following additional config is required/selected by the TSN subsystem:

CONFIG_NET_SWITCHDEV
CONFIG_STP
CONFIG_NETFILTER

Devicetree

TSN subsystem DT documentation can be found here: Documentation/devicetree/bindings/staging/net/xilinx_tsn.txt

For TSN TEMAC, please refer to Documentation/devicetree/bindings/staging/net/xilinx-tsn-ethernet.txt

For TSN Switch, please refer to Documentation/devicetree/bindings/staging/net/xilinx_tsn_switch.txt

For TSN Endpoint, please refer to Documentation/devicetree/bindings/staging/net/xilinx_tsn_ep.txt

For TSN Extended Endpoint, please refer to Documentation/devicetree/bindings/staging/net/xilinx_tsn_ep_ex.txt

Please refer to PL Ethernet and DMA documentation for additional information: Documentation/devicetree/bindings/net/xlnx,axi-ethernet.yaml

For more details on phy bindings please refer "Documentation/devicetree/bindings/net/ethernet-phy.yaml"

Note:

  • TSN devicetree from DTG flow is automatically generated for an RGMII PHY at address 0. For custom boards or design, please update your own device tree node as per the the devicetree documentation mentioned above.

  • Please note that xlnx, packet-switch DT property is now used instead of packet-switch; the latter will be deprecated shortly. This DT property is used to identify packet switch feature enablement in TSN IP subsystem.

NOTE: In AMD 2025.1 tools, the System Device Tree (SDT) flow is the default. All new TSN and other software features are tested and validated using the SDT flow instead of the legacy flow.

TSN System

  • Xilinx’s TSN IP Switch has three ports Endpoint (Port 0), MAC1 (Port 1) and MAC2 (Port 2)

  • Endpoint is connected to MCDMA (Multichannel DMA), each MCDMA channel is a dedicated channel for each type of traffic, i.e. Best Effort, Scheduled Traffic and Reserved. There could be other use cases where there would be separate channels for management traffic

  • MAC1 is connected to external world by PHY1

  • MAC2 is connected to external world by PHY2      





Traffic Classes

TSN IP supports multiple queues and traffic class configurations as listed below:

a. 3 queue or 3 traffic class system:

         1. Best Effort

         2. Scheduled

         3. Reserved

b. 2 queue/2 traffic class system 

          1. Best Effort

          2. Scheduled

c. 8 queue with 3 traffic class system (starting from 2025.1)

         1. Best Effort

         2. Scheduled

         3. Reserved

PCP and Traffic Class

The vlan pcp of the ethernet frame is used to identify the traffic class by the HW. By default, pcp of 4 is mapped to ST and pcp’s of 2 and 3 are mapped to RES(reserved). If pcp is any other or if frame has no vlan tag, its considered as BE.

2019.x and earlier releases:

This default mapping can be changed by kernel command line option, in uEnv.txt.

For eg.

             bootargs=console=ttyPS0,115200 xilinx_tsn_ep.st_pcp=5 xilinx_tsn_ep.res_pcp=2,3 root=/dev/mmcblk0p2 rw rootwait earlyprintk

2020.x and later releases:

The arguments in boot.scr determine PCP mapping. The default values remain same as mentioned above.

To change the PCP, edit the file <TOP_DIR>/sources/meta-xilinx-tsn/recipes-bsp/u-boot/uboot-zynq-scr/boot.cmd.sd.<boardname>.
For example, the following command line maps a pcp of 1 to ST traffic, a pcp of 4 to RES traffic, and the
rest of the pcps to BE traffic:
bootargs=console=ttyPS0,115200 xilinx_tsn_ep.st_pcp=1 xilinx_tsn_ep.res_pcp=4
root=/dev/mmcblk0p2 rw rootwait earlyprintk

The following command line maps pcps of 2 and 3 to ST traffic, a pcp of 1 to RES traffic, and the rest of the pcps to BE traffic.
bootargs=console=ttyPS0,115200 xilinx_tsn_ep.st_pcp=2,3 xilinx_tsn_ep.res_pcp=1
root=/dev/mmcblk0p2 rw rootwait earlyprintk

After changing the PCP values, source the bitbake environment and run bitbake build again:
#source setupsdk
#bitbake core-image-minimal

CAUTION: Do not edit the boot.scr file directly.

2025.1 and later releases:

In the legacy design where num_priorities <= 3, users can configure the PCP (Priority Code Point) values for Scheduled Traffic (ST) and Reserved (RES) traffic by passing boot arguments.
In the driver by default, ST traffic is mapped to PCP value 4, while RES traffic is mapped to PCP values 2 and 3.
If a user wants to change the default ST PCP value from 4 to any other value in the range 0 to 7, they should pass the desired value using the boot argument xilinx_emac_tsn.st_pcp=<0-7>.
Similarly, to override the default RES PCP values, the user can pass the required values using xilinx_emac_tsn.res_pcp=<0-7,...>.
NOTE:
From release 2025.1 onwards, the module name changed from xilinx_tsn_ep to xilinx_emac_tsn as part of the support for a modular driver architecture.
Please make sure to use the updated module name starting from the 2025.1 release.

In flexible queues mode (i.e., when num_priorities > 3), the default mapping of PCP to traffic classes cannot be changed. In this configuration, PCP values are assigned in a 1:1 to their corresponding priority queues, limited to the maximum number of supported priorities. Any remaining PCP values are directed to priority queue 0. For instance, if the system is configured to support four priorities, the mapping would be as follows: PCP0 is assigned to priority queue 0, PCP1 to priority queue 1, PCP2 to priority queue 2, and PCP3 to priority queue 3. All other PCP values are then allocated to priority queue 0.

Generating TSN Traffic:

Generating TSN Traffic, can be done by using raw sockets, where you can create ethernet frame with relevant pcp. One such implementation is tsn_talker provided as part of TSN Yocto SW release.

Converting Legacy Applications to TSN

Sometimes users need port legacy applications to send/receive TSN Traffic without having to change/modify them. For example, an application which only uses L3 layer (IP) to communicate shall not have capabilities to insert pcp/vlan into the frame. To solve this, Xilinx TSN Solution has IP interception kernel module support, to seamlessly transition legacy applications to use TSN technology. See "Running IPIC" section for more details.

Test Procedure

PTP Profiles Supported

TSN IP has support for following profiles:

a. 1588v1 and 1588v2

b. Power Profile

c. 802.1AS

d. 802.1ASREV



TSN driver and SW daemon (ptp4l and openAvnu/gptp) support is available for :

a. 1588v2

b. 802.1AS

c. 802.1ASREV (not all features may be available. See ptp4l/openAvnu documentation).

Running gPTP(802.1AS):

       gPTP daemon can be run in two ways. One way is to run it from OpenAvnu, and the other is to run it from ptp4linux. Latter is preferred as it prints rms values at slave to identify sync with master.

  • Running gPTP daemon from OpenAvnu:

          From the Intel card PC machine launch gPTP daemon as follows:

          #Open-AVB/daemons/gptp/linux/build/obj/daemon_cl enp4s0 –S

          From the Xilinx board launch PTP daemon as follows:

          #daemon_cl eth1 –S

          [1] 186
          ERROR at 636 in ../src/linux_hal_common.cpp: Group ptp not found, will try root (0) instead
          Using clock device: /dev/ptp0
          Starting PDelay
          root@Xilinx-ZCU102-2016_1:~# AsCapable: Enabled
         *** Announce Timeout Expired - Becoming Master
         New Grandmaster "00:0A:35:FF:FE:00:01:0E" (previous "00:00:00:00:00:00:00:00")
         <<END>>

  • Running gPTP daemon from ptp4linux:

         From the Xilinx board launch PTP daemon as follows:

         #ptp4l -P -2 -H -i eth1 -p /dev/ptp0 –s -m -f /usr/sbin/ptp4l_slave.conf

         Download PTP daemon from https://sourceforge.net/p/linuxptp/ and compile to get ptp4l binary in Intel card PC. Use gPTP.cfg or default.cfg file present in the linuxptp source code.

         From the Intel card PC launch PTP daemon as follows:

         (Use /usr/bin/ptp4l_master.conf from the board on PC)

         #ptp4l -P -2 -H -i enp4s0 -p /dev/ptp0 -m -f ptp4l_master.conf

        Upon successful synchronization, RMS values prints at the slave would be as follows:

        root@zcu102-zynqmp:~# ptp4l -P -2 -H -i eth1 /dev/ptp0 -s -m -f /usr/sbin/ptp4l_slave.conf

        ptp4l[7940.770]: selected /dev/ptp0 as PTP clock

        ptp4l[7940.800]: driver changed our HWTSTAMP options

        ptp4l[7940.800]: tx_type   1 not 1

        ptp4l[7940.800]: rx_filter 1 not 12

        ptp4l[7940.800]: port 1: INITIALIZING to LISTENING on INITIALIZE

        ptp4l[7940.800]: port 0: INITIALIZING to LISTENING on INITIALIZE

        ptp4l[7948.772]: port 1: LISTENING to MASTER on ANNOUNCE_RECEIPT_TIMEOUT_EXPIRES

        ptp4l[7948.772]: selected best master clock 000a35.fffe.00010e

        ptp4l[7948.772]: assuming the grand master role

        ptp4l[7949.452]: port 1: new foreign master a0369f.fffe.684c96-1

        ptp4l[7953.452]: selected best master clock a0369f.fffe.684c96

        ptp4l[7953.452]: port 1: MASTER to UNCALIBRATED on RS_SLAVE

        ptp4l[7953.951]: port 1: UNCALIBRATED to SLAVE on MASTER_CLOCK_SELECTED

        ptp4l[7954.701]: rms 1732 max 2297 freq -100287 +/- 1208 delay   509 +/-   0

        ptp4l[7955.701]: rms  326 max  499 freq -101341 +/- 438 delay   509 +/-   0

        ptp4l[7956.702]: rms  545 max  579 freq -102323 +/- 151 delay   509 +/-   0

        ptp4l[7957.702]: rms  343 max  463 freq -102512 +/-   9 delay   509 +/-   0

        ptp4l[7958.702]: rms  118 max  193 freq -102419 +/-  43 delay   509 +/-   0

        Note:

  • Currently 1 step ptp mode is not supported in software

  • The roles of master and slave can be changed by changing the priority values. A low priority implies it is a master and a higher priority implies it is a slave.

  • By default the MAC ports link speed is 1Gbps, use the following command to set it at 100Mbps, incase 100Mbps setting is required

    # mii-tool -F 100baseTx-FD eth1

    Change the ptp4l config files (/usr/sbin/ptp4l_slave.conf and /usr/sbin/ptp4l_master.conf) parameter neighborPropDelayThresh as below
    neighborPropDelayThresh 2000       - for 100Mbps link speed
    or
    neighborPropDelayThresh 800         - for 1Gbps link speed

Running two gPTP time domains

This section describes how to run two independent gPTP (802.1AS) time domains on TSN designs that use a dual-RTC architecture with a free-running timestamping clock and virtual clocks.

Overview

In dual-RTC mode, RTC2 is used exclusively for PTP packet timestamping and operates as a free-running clock. Two virtual clocks are created from RTC2 and exposed as separate PTP devices:

  • Wall clock — used as a general system/wall clock time domain.

  • Working clock — used as the TSN working clock time domain.

  • RTC1 drives the QBV scheduler and TADMA IP and must be synchronized to the working clock virtual clock using phc2sys.

The Common Mean Link Delay Service (CMLDS) is used to share link delay measurements across both domains, avoiding redundant P2P delay measurements. Each domain runs its own ptp4l instance, while a separate CMLDS server ptp4l instance handles shared link delay computation.

Prerequisites

  • TSN IP design with dual-RTC mode enabled (separate RTC for timestamping and scheduling).

  • Configuration files copied to the target (see below). Replace eth0 with the appropriate TSN network interface name.

Configuration Files

The following configuration files are required. Create these files on the target board before running the test:

  • master_server.conf / slave_server.conf — CMLDS server configuration

  • master_wall_clock.conf / slave_wall_clock.conf — wall clock domain (domain 0) gPTP configuration

  • master_working_clock.conf / slave_working_clock.conf — working clock domain (domain 1) gPTP configuration

master_server.conf

[global] priority1 248 priority2 249 ptp_dst_mac 01:80:C2:00:00:0E p2p_dst_mac 01:80:C2:00:00:0E logAnnounceInterval 1 logSyncInterval -3 follow_up_info 1 announceReceiptTimeout 3 syncReceiptTimeout 3 neighborPropDelayThresh 800 min_neighbor_prop_delay -20000000 network_transport L2 delay_mechanism P2P tx_timestamp_timeout 10 # CMLDS free_running 1 ignore_transport_specific 1 transportSpecific 2 uds_address /var/run/cmlds_server delay_mechanism P2P # # 802.1AS2020 default for allowedLostResponses # allowedLostResponses 9

slave_server.conf

[global] transportSpecific 1 priority1 250 priority2 251 ptp_dst_mac 01:80:C2:00:00:0E p2p_dst_mac 01:80:C2:00:00:0E logAnnounceInterval 1 logSyncInterval -3 follow_up_info 1 announceReceiptTimeout 3 syncReceiptTimeout 3 neighborPropDelayThresh 800 min_neighbor_prop_delay -20000000 network_transport L2 delay_mechanism P2P tx_timestamp_timeout 10 # CMLDS free_running 1 ignore_transport_specific 1 transportSpecific 2 uds_address /var/run/cmlds_server delay_mechanism P2P # # 802.1AS2020 default for allowedLostResponses # allowedLostResponses 9

master_wall_clock.conf

[global] transportSpecific 1 priority1 248 priority2 249 ptp_dst_mac 01:80:C2:00:00:0E p2p_dst_mac 01:80:C2:00:00:0E logAnnounceInterval 1 logSyncInterval -3 follow_up_info 1 announceReceiptTimeout 3 syncReceiptTimeout 3 neighborPropDelayThresh 800 min_neighbor_prop_delay -20000000 network_transport L2 tx_timestamp_timeout 10 delay_mechanism COMMON_P2P # # UDS addresses # cmlds.client_address /var/run/cmlds-client-1 cmlds.server_address /var/run/cmlds_server uds_address /var/run/cmlds-domain-1 clockIdentity 000a35.fffe.EE011e

slave_wall_clock.conf

[global] transportSpecific 1 priority1 250 priority2 251 ptp_dst_mac 01:80:C2:00:00:0E p2p_dst_mac 01:80:C2:00:00:0E logAnnounceInterval 1 logSyncInterval -3 follow_up_info 1 announceReceiptTimeout 3 syncReceiptTimeout 3 neighborPropDelayThresh 800 min_neighbor_prop_delay -20000000 network_transport L2 tx_timestamp_timeout 10 delay_mechanism COMMON_P2P # # UDS addresses # cmlds.client_address /var/run/cmlds-client-1 cmlds.server_address /var/run/cmlds_server uds_address /var/run/cmlds-domain-1 clockIdentity 000a35.fffe.55012e

master_working_clock.conf

[global] transportSpecific 1 priority1 248 priority2 249 ptp_dst_mac 01:80:C2:00:00:0E p2p_dst_mac 01:80:C2:00:00:0E logAnnounceInterval 1 logSyncInterval -3 follow_up_info 1 announceReceiptTimeout 3 syncReceiptTimeout 3 neighborPropDelayThresh 800 min_neighbor_prop_delay -20000000 network_transport L2 tx_timestamp_timeout 10 delay_mechanism COMMON_P2P # # UDS addresses # cmlds.client_address /var/run/cmlds-client-2 cmlds.server_address /var/run/cmlds_server uds_address /var/run/cmlds-domain-2 clockIdentity 000a35.fffe.EF011e domainNumber 1

slave_working_clock.conf

[global] transportSpecific 1 priority1 250 priority2 251 ptp_dst_mac 01:80:C2:00:00:0E p2p_dst_mac 01:80:C2:00:00:0E logAnnounceInterval 1 logSyncInterval -3 follow_up_info 1 announceReceiptTimeout 3 syncReceiptTimeout 3 neighborPropDelayThresh 800 min_neighbor_prop_delay -20000000 network_transport L2 delay_mechanism P2P tx_timestamp_timeout 10 delay_mechanism COMMON_P2P # # UDS addresses # cmlds.client_address /var/run/cmlds-client-2 cmlds.server_address /var/run/cmlds_server uds_address /var/run/cmlds-domain-2 clockIdentity 000a35.fffe.56012e domainNumber 1

Board-to-Board Setup

Connect two TSN boards directly (e.g., ZCU102 board-to-board). Designate one board as master and the other as slave. On each board, identify the timestamping PHC and QBV PHC indices using ethtool -T <interface>. The timestamping PHC index is the base PTP Hardware Clock number; the QBV PHC index is the next consecutive index.

On Master

ts_clock_phc_idx=$(ethtool -T eth0 | awk '/^PTP Hardware Clock/ {print $NF}') qbv_clock_phc_idx=$(ethtool -T eth0 | awk '/^PTP Hardware Clock/ {print $NF+1}') # Enable the 2 virtual clocks echo 2 > /sys/class/net/eth0/device/ptp/ptp${ts_clock_phc_idx}/n_vclocks wall_clock_phc_idx=$(ls /sys/class/net/eth0/device/ptp/ptp$(ethtool -T eth0 | awk '/^PTP Hardware Clock/ {print $NF}') | awk '/^ptp[0-9]+/{gsub(/ptp/,""); print}' | sort -n | sed -n '1p') working_clock_phc_idx=$(ls /sys/class/net/eth0/device/ptp/ptp$(ethtool -T eth0 | awk '/^PTP Hardware Clock/ {print $NF}') | awk '/^ptp[0-9]+/{gsub(/ptp/,""); print}' | sort -n | sed -n '2p') # Start CMLDS server ptp4l -2 -H -m -i eth0 -f master_server.conf & # Launch ptp4l for the wall clock time domain ptp4l -2 -H -m -i eth0 -f master_wall_clock.conf -p /dev/ptp${wall_clock_phc_idx} & # Launch ptp4l for the working clock time domain ptp4l -2 -H -m -i eth0 -f master_working_clock.conf -p /dev/ptp${working_clock_phc_idx} & # Sync working clock phc to QBV clock phc phc2sys -s /dev/ptp${working_clock_phc_idx} -c /dev/ptp${qbv_clock_phc_idx} -O0 &

On Slave

ts_clock_phc_idx=$(ethtool -T eth0 | awk '/^PTP Hardware Clock/ {print $NF}') qbv_clock_phc_idx=$(ethtool -T eth0 | awk '/^PTP Hardware Clock/ {print $NF+1}') # Enable the 2 virtual clocks echo 2 > /sys/class/net/eth0/device/ptp/ptp${ts_clock_phc_idx}/n_vclocks wall_clock_phc_idx=$(ls /sys/class/net/eth0/device/ptp/ptp$(ethtool -T eth0 | awk '/^PTP Hardware Clock/ {print $NF}') | awk '/^ptp[0-9]+/{gsub(/ptp/,""); print}' | sort -n | sed -n '1p') working_clock_phc_idx=$(ls /sys/class/net/eth0/device/ptp/ptp$(ethtool -T eth0 | awk '/^PTP Hardware Clock/ {print $NF}') | awk '/^ptp[0-9]+/{gsub(/ptp/,""); print}' | sort -n | sed -n '2p') # Start CMLDS server ptp4l -2 -H -m -i eth0 -f slave_server.conf & # Launch ptp4l for the wall clock time domain ptp4l -2 -H -m -i eth0 -f slave_wall_clock.conf -p /dev/ptp${wall_clock_phc_idx} & # Launch ptp4l for the working clock time domain ptp4l -2 -H -m -i eth0 -f slave_working_clock.conf -p /dev/ptp${working_clock_phc_idx} & # Sync working clock phc to QBV clock phc phc2sys -s /dev/ptp${working_clock_phc_idx} -c /dev/ptp${qbv_clock_phc_idx} -O0 &

Upon successful synchronization, the slave side logs would be as follows:

CMLDS server (slave)

        ptp4l[71033.948]: port 1 (eth0): INITIALIZING to LISTENING on INIT_COMPLETE

        ptp4l[71033.948]: port 0 (/var/run/cmlds_server): INITIALIZING to LISTENING on INIT_COMPLETE

        ptp4l[71033.948]: port 0 (/var/run/ptp4lro): INITIALIZING to LISTENING on INIT_COMPLETE

        ptp4l[71037.593]: port 1 (eth0): new foreign master 000a35.fffe.00011e-1

        ptp4l[71040.161]: port 1 (eth0): LISTENING to MASTER on ANNOUNCE_RECEIPT_TIMEOUT_EXPIRES

        ptp4l[71040.161]: selected local clock 000a35.fffe.00012e as best master

        ptp4l[71040.161]: port 1 (eth0): assuming the grand master role

        ptp4l[71041.593]: selected best master clock 000a35.fffe.00011e

        ptp4l[71041.593]: port 1 (eth0): MASTER to UNCALIBRATED on RS_SLAVE

        ptp4l[71043.594]: master offset 1060065829 s0 freq +952 path delay 395

        ptp4l[71045.594]: master offset 1060067709 s0 freq +940 path delay 395

        ptp4l[71047.595]: master offset 1060069613 s0 freq +952 path delay 395

        ptp4l[71049.595]: master offset 1060071517 s0 freq +952 path delay 395

        ptp4l[71051.596]: master offset 1060073421 s0 freq +952 path delay 395

        ptp4l[71053.596]: master offset 1060075333 s0 freq +956 path delay 395

        ptp4l[71055.596]: master offset 1060077245 s0 freq +956 path delay 395

        ptp4l[71057.597]: master offset 1060079157 s0 freq +956 path delay 395

        ptp4l[71059.597]: master offset 1060081093 s0 freq +968 path delay 395

        ptp4l[71061.598]: master offset 1060083037 s0 freq +972 path delay 395

        ptp4l[71063.598]: master offset 1060084965 s0 freq +964 path delay 395

        ptp4l[71065.598]: master offset 1060086909 s0 freq +972 path delay 395

        ptp4l[71067.599]: master offset 1060088861 s0 freq +976 path delay 395

        ptp4l[71069.599]: master offset 1060090807 s0 freq +972 path delay 393

        ptp4l[71071.600]: master offset 1060092757 s0 freq +976 path delay 395

        ptp4l[71073.600]: master offset 1060094709 s0 freq +976 path delay 395

        ptp4l[71075.600]: master offset 1060096645 s0 freq +968 path delay 395

        ptp4l[71077.601]: master offset 1060098589 s0 freq +972 path delay 395

        ptp4l[71079.601]: master offset 1060100543 s0 freq +976 path delay 393

        ptp4l[71081.601]: master offset 1060102497 s0 freq +976 path delay 391

        ptp4l[71083.602]: master offset 1060104449 s0 freq +976 path delay 391

        ptp4l[71085.602]: master offset 1060106399 s0 freq +976 path delay 393

        ptp4l[71087.603]: master offset 1060108351 s0 freq +976 path delay 393

        ptp4l[71089.603]: master offset 1060110309 s0 freq +980 path delay 395

        ptp4l[71091.603]: master offset 1060112247 s0 freq +968 path delay 393

        ptp4l[71093.604]: master offset 1060114193 s0 freq +972 path delay 391

        ptp4l[71095.604]: master offset 1060116145 s0 freq +976 path delay 391

        ptp4l[71097.605]: master offset 1060118105 s0 freq +980 path delay 391

Wall clock domain (slave)

        ptp4l[72805.607]: selected /dev/ptp3 as PTP clock

        ptp4l[72805.608]: port 1 (eth0): /dev/ptp3 is virtual clock

        ptp4l[72805.632]: port 1 (eth0): INITIALIZING to LISTENING on INIT_COMPLETE

        ptp4l[72805.632]: port 0 (/var/run/cmlds-domain-1): INITIALIZING to LISTENING on INIT_COMPLETE

        ptp4l[72805.632]: uds: removed existing /var/run/ptp4lro

        ptp4l[72805.632]: port 0 (/var/run/ptp4lro): INITIALIZING to LISTENING on INIT_COMPLETE

        ptp4l[72807.398]: port 1 (eth0): new foreign master 000a35.fffe.ee011e-1

        ptp4l[72811.398]: selected best master clock 000a35.fffe.ee011e

        ptp4l[72811.399]: port 1 (eth0): LISTENING to UNCALIBRATED on RS_SLAVE

        ptp4l[72812.277]: port 1 (eth0): UNCALIBRATED to SLAVE on MASTER_CLOCK_SELECTED

        ptp4l[72812.902]: rms 899423304596416512 max 1798846609192833280 freq +881 +/- 333 delay 395 +/- 0

        ptp4l[72813.903]: rms 20 max 25 freq +977 +/- 4 delay 395 +/- 0

        ptp4l[72814.903]: rms 10 max 15 freq +975 +/- 4 delay 395 +/- 0

        ptp4l[72815.903]: rms 4 max 9 freq +984 +/- 6 delay 395 +/- 0

        ptp4l[72816.903]: rms 4 max 7 freq +989 +/- 4 delay 395 +/- 0

        ptp4l[72817.903]: rms 4 max 7 freq +988 +/- 5 delay 395 +/- 0

        ptp4l[72818.904]: rms 5 max 9 freq +996 +/- 4 delay 395 +/- 0

        ptp4l[72819.904]: rms 3 max 7 freq +990 +/- 4 delay 395 +/- 0

        ptp4l[72820.904]: rms 5 max 8 freq +987 +/- 6 delay 395 +/- 0

        ptp4l[72821.904]: rms 6 max 11 freq +996 +/- 6 delay 395 +/- 0

        ptp4l[72822.904]: rms 8 max 12 freq +1008 +/- 4 delay 393 +/- 0

        ptp4l[72823.905]: rms 4 max 8 freq +999 +/- 5 delay 395 +/- 0

        ptp4l[72824.905]: rms 4 max 7 freq +998 +/- 5 delay 395 +/- 0

        ptp4l[72825.905]: rms 6 max 10 freq +990 +/- 5 delay 395 +/- 0

        ptp4l[72826.905]: rms 4 max 8 freq +989 +/- 4 delay 395 +/- 0

        ptp4l[72827.905]: rms 4 max 7 freq +992 +/- 5 delay 395 +/- 0

        ptp4l[72828.905]: rms 5 max 9 freq +984 +/- 5 delay 395 +/- 0

        ptp4l[72829.906]: rms 4 max 6 freq +982 +/- 3 delay 395 +/- 0

        ptp4l[72830.906]: rms 5 max 9 freq +988 +/- 7 delay 395 +/- 0

        ptp4l[72831.906]: rms 6 max 10 freq +991 +/- 7 delay 395 +/- 0

        ptp4l[72832.906]: rms 2 max 4 freq +988 +/- 3 delay 395 +/- 0

        ptp4l[72833.907]: rms 3 max 5 freq +986 +/- 3 delay 395 +/- 0

        ptp4l[72834.907]: rms 4 max 7 freq +989 +/- 6 delay 395 +/- 0

        ptp4l[72835.907]: rms 4 max 8 freq +990 +/- 6 delay 395 +/- 0

        ptp4l[72836.907]: rms 3 max 6 freq +992 +/- 4 delay 395 +/- 0

        ptp4l[72837.907]: rms 4 max 7 freq +991 +/- 6 delay 395 +/- 0

        ptp4l[72838.908]: rms 4 max 8 freq +997 +/- 5 delay 395 +/- 0

        ptp4l[72839.908]: rms 4 max 6 freq +997 +/- 5 delay 395 +/- 0

        ptp4l[72840.908]: rms 3 max 6 freq +1000 +/- 4 delay 395 +/- 0

        ptp4l[72841.908]: rms 6 max 10 freq +992 +/- 7 delay 395 +/- 0

Working clock domain (slave)

        ptp4l[75767.657]: selected /dev/ptp4 as PTP clock

        ptp4l[75767.658]: port 1 (eth0): /dev/ptp4 is virtual clock

        ptp4l[75767.688]: port 1 (eth0): INITIALIZING to LISTENING on INIT_COMPLETE

        ptp4l[75767.688]: port 0 (/var/run/cmlds-domain-2): INITIALIZING to LISTENING on INIT_COMPLETE

        ptp4l[75767.688]: uds: removed existing /var/run/ptp4lro

        ptp4l[75767.688]: port 0 (/var/run/ptp4lro): INITIALIZING to LISTENING on INIT_COMPLETE

        ptp4l[75769.983]: port 1 (eth0): new foreign master 000a35.fffe.ef011e-1

        ptp4l[75773.983]: selected best master clock 000a35.fffe.ef011e

        ptp4l[75773.983]: port 1 (eth0): LISTENING to UNCALIBRATED on RS_SLAVE

        ptp4l[75774.359]: port 1 (eth0): UNCALIBRATED to SLAVE on MASTER_CLOCK_SELECTED

        ptp4l[75774.984]: rms 915191299839643136 max 1830382599679286528 freq +944 +/- 357 delay 395 +/- 0

        ptp4l[75775.984]: rms 9 max 13 freq +1066 +/- 4 delay 395 +/- 0

        ptp4l[75776.985]: rms 6 max 9 freq +1065 +/- 4 delay 395 +/- 0

        ptp4l[75777.985]: rms 4 max 7 freq +1068 +/- 5 delay 395 +/- 0

        ptp4l[75778.985]: rms 5 max 6 freq +1067 +/- 6 delay 395 +/- 0

        ptp4l[75779.985]: rms 4 max 8 freq +1069 +/- 6 delay 395 +/- 0

        ptp4l[75780.985]: rms 4 max 7 freq +1074 +/- 3 delay 395 +/- 0

        ptp4l[75781.986]: rms 4 max 7 freq +1074 +/- 6 delay 395 +/- 0

        ptp4l[75782.986]: rms 4 max 6 freq +1071 +/- 5 delay 395 +/- 0

        ptp4l[75783.986]: rms 4 max 6 freq +1069 +/- 5 delay 395 +/- 0

        ptp4l[75784.986]: rms 4 max 8 freq +1068 +/- 6 delay 395 +/- 0

        ptp4l[75785.986]: rms 4 max 7 freq +1071 +/- 5 delay 395 +/- 0

        ptp4l[75786.987]: rms 3 max 6 freq +1070 +/- 5 delay 395 +/- 0

        ptp4l[75787.987]: rms 3 max 7 freq +1067 +/- 4 delay 395 +/- 0

        ptp4l[75788.987]: rms 4 max 8 freq +1063 +/- 5 delay 395 +/- 0

        ptp4l[75789.987]: rms 4 max 7 freq +1061 +/- 5 delay 395 +/- 0

        ptp4l[75790.987]: rms 4 max 8 freq +1065 +/- 5 delay 395 +/- 0

        ptp4l[75791.987]: rms 3 max 5 freq +1065 +/- 4 delay 395 +/- 0

        ptp4l[75792.988]: rms 3 max 4 freq +1066 +/- 4 delay 393 +/- 0

        ptp4l[75793.988]: rms 3 max 7 freq +1069 +/- 4 delay 393 +/- 0

        ptp4l[75794.988]: rms 5 max 8 freq +1070 +/- 6 delay 391 +/- 0

        ptp4l[75795.988]: rms 3 max 4 freq +1068 +/- 4 delay 393 +/- 0

        ptp4l[75796.988]: rms 6 max 14 freq +1068 +/- 8 delay 391 +/- 0

        ptp4l[75797.989]: rms 5 max 9 freq +1060 +/- 3 delay 391 +/- 0

        ptp4l[75798.989]: rms 3 max 4 freq +1065 +/- 3 delay 391 +/- 0

        ptp4l[75799.989]: rms 4 max 6 freq +1067 +/- 5 delay 391 +/- 0

        ptp4l[75800.989]: rms 4 max 6 freq +1071 +/- 4 delay 391 +/- 0

        ptp4l[75801.989]: rms 4 max 8 freq +1072 +/- 5 delay 391 +/- 0

        ptp4l[75802.990]: rms 2 max 4 freq +1070 +/- 3 delay 391 +/- 0

        ptp4l[75803.990]: rms 6 max 9 freq +1063 +/- 6 delay 391 +/- 0

        ptp4l[75804.990]: rms 3 max 5 freq +1067 +/- 4 delay 393 +/- 0

        ptp4l[75805.990]: rms 5 max 8 freq +1074 +/- 4 delay 391 +/- 0

Notes

  • One-step synchronization is not supported when using virtual clocks.

  • Each ptp4l domain instance must be bound to its respective virtual clock PHC using the -p /dev/ptp<N> option.

  • The CMLDS server ptp4l instance must be started before the domain ptp4l instances.

Running PTP 1588v2 :

  • PTPv2 uses Best Master Clock algorithm to determine which clock is of highest quality(grand master) within the network to create master/slave hierarchy and synchronizes all other nodes with grand master. To make a node master, priority field in configuration file should have the least value.

  • PTPv2 can be run over L2 or UDP. When run over UDP, it can be run in multicast mode on ep + switch systems and in both multicast and unicast modes on ep only systems.

  • To Run on Intel Card PC, download PTP daemon from https://sourceforge.net/p/linuxptp/ and compile to get ptp4l binary. Copy master/slave configuration files to linuxptp folder and launch ptp4l daemon from the folder as mentioned below.

  • To run PTPv2 over L2:

    Peer to Peer(P2P) mechanism:

    To run as master on zcu102 or zc702:

    ptp4l -P -2 -H -i eth1 -p /dev/ptp0 -m -f /usr/sbin/ptp4l_master_v2_l2.conf

    To run as slave on zcu102 or zc702:

    ptp4l -P -2 -H -i eth1 -p /dev/ptp0 -m -f /usr/sbin/ptp4l_slave_v2_l2.conf

    To run as master on Intel Card PC:

    ptp4l -P -2 -H -i eth1 -p /dev/ptp0 -m -f ptp4l_master_v2_l2.conf

    To run as slave on Intel Card PC:

    ptp4l -P -2 -H -i eth1 -p /dev/ptp0 -m -f ptp4l_slave_v2_l2.conf

    End to End(E2E) mechanism:

    To run as master on zcu102 or zc702:

    ptp4l -E -2 -H -i eth1 -p /dev/ptp0 -m -f /usr/sbin/ptp4l_master_v2_l2.conf

    To run as slave on zcu102 or zc702:

    ptp4l -E -2 -H -i eth1 -p /dev/ptp0 -m -f /usr/sbin/ptp4l_slave_v2_l2.conf

    To run as master on Intel Card PC:

    ptp4l -E -2 -H -i eth1 -p /dev/ptp0 -m -f ptp4l_master_v2_l2.conf

    To run as slave on Intel Card PC:

    ptp4l -E -2 -H -i eth1 -p /dev/ptp0 -m -f ptp4l_slave_v2_l2.conf



    PTPv2 over UDP and in multicast mode:

    Peer to Peer(P2P) mechanism:

    To run as master on zcu102 or zc702:

    ptp4l -P -4 -H -i eth1 -p /dev/ptp0 -m -f /usr/sbin/ptp4l_master_v2_udp_multicast.conf

    To run as slave on zcu102 or zc702:

    ptp4l -P -4 -H -i eth1 -p /dev/ptp0 -m -f /usr/sbin/ptp4l_slave_v2_udp_multicast.conf

    To run as master on Intel Card PC:

    ptp4l -P -4 -H -i eth1 -p /dev/ptp0 -m -f ptp4l_master_v2_udp_multicast.conf

    To run as slave on Intel Card PC:

    ptp4l -P -4 -H -i eth1 -p /dev/ptp0 -m -f ptp4l_slave_v2_udp_multicast.conf

    End to End(E2E) mechanism:

    To run as master on zcu102 or zc702:

    ptp4l -E -4 -H -i eth1 -p /dev/ptp0 -m -f /usr/sbin/ptp4l_master_v2_udp_multicast.conf

    To run as slave on zcu102 or zc702:

    ptp4l -E -4 -H -i eth1 -p /dev/ptp0 -m -f /usr/sbin/ptp4l_slave_v2_udp_multicast.conf

    To run as master on Intel Card PC:

    ptp4l -E -4 -H -i eth1 -p /dev/ptp0 -m -f ptp4l_master_v2_udp_multicast.conf

    To run as slave on Intel Card PC:

    ptp4l -E -4 -H -i eth1 -p /dev/ptp0 -m -f ptp4l_slave_v2_udp_multicast.conf



    PTPv2 over UDP and in unicast mode:

    Peer to Peer(P2P) mechanism:

    To run as master on zcu102 or zc702:

    ptp4l -P -4 -H -i eth1 -p /dev/ptp0 -m -f /usr/sbin/ptp4l_master_v2_udp_unicast_p2p.conf

    To run as slave on zcu102 or zc702:

    'peer_address' field of /usr/sbin/ptp4l_slave_v2_udp_unicast_p2p.conf should be set to the

    IP address of master

    ptp4l -P -4 -H -i eth1 -p /dev/ptp0 -m -f /usr/sbin/ptp4l_slave_v2_udp_unicast_p2p.conf

    To run as master on Intel Card PC:

    ptp4l -P -4 -H -i eth1 -p /dev/ptp0 -m -f ptp4l_master_v2_udp_unicast_p2p.conf

    To run as slave on Intel Card PC:

    'peer_address' field of ptp4l_slave_v2_udp_unicast_p2p.conf should be set to the

    IP address of master

    ptp4l -P -4 -H -i eth1 -p /dev/ptp0 -m -f ptp4l_slave_v2_udp_unicast_p2p.conf

    End to End(E2E) mechanism:

    To run as master on zcu102 or zc702:

    ptp4l -E -4 -H -i eth1 -p /dev/ptp0 -m -f /usr/sbin/ptp4l_master_v2_udp_unicast_e2e.conf

    To run as slave on zcu102 or zc702:

    'UDPv4' field of /usr/sbin/ptp4l_slave_v2_udp_unicast_e2e.conf should be set to the

    IP address of master

    ptp4l -E -4 -H -i eth1 -p /dev/ptp0 -m -f /usr/sbin/ptp4l_slave_v2_udp_unicast_e2e.conf

    To run as master on Intel Card PC:

    ptp4l -E -4 -H -i eth1 -p /dev/ptp0 -m -f ptp4l_master_v2_udp_unicast_e2e.conf

    To run as slave on Intel Card PC:

    'UDPv4' field of ptp4l_slave_v2_udp_unicast_e2e.conf should be set to the

    IP address of master

    ptp4l -E -4 -H -i eth1 -p /dev/ptp0 -m -f ptp4l_slave_v2_udp_unicast_e2e.conf



    On successful synchronization, logs at the slave would be as follows:

    ptp4l[765.873]: selected /dev/ptp0 as PTP clock

    ptp4l[765.960]: driver rejected most general HWTSTAMP filter

    ptp4l[765.960]: port 1: INITIALIZING to LISTENING on INIT_COMPLETE

    ptp4l[765.960]: port 0: INITIALIZING to LISTENING on INIT_COMPLETE

    ptp4l[772.710]: port 1: LISTENING to MASTER on ANNOUNCE_RECEIPT_TIMEOUT_EXPIRES

    ptp4l[772.710]: selected local clock 000a35.fffe.00012e as best master

    ptp4l[772.710]: assuming the grand master role

    ptp4l[775.065]: port 1: new foreign master 000a35.fffe.00013e-1

    ptp4l[779.065]: selected best master clock 000a35.fffe.00013e

    ptp4l[779.065]: port 1: MASTER to UNCALIBRATED on RS_SLAVE

    ptp4l[780.064]: master offset 3409342692 s0 freq      +0 path delay       396

    ptp4l[781.065]: master offset 3409344460 s1 freq   +1768 path delay       396

    ptp4l[782.065]: master offset       -373 s2 freq   +1395 path delay       396

    ptp4l[782.065]: port 1: UNCALIBRATED to SLAVE on MASTER_CLOCK_SELECTED

    ptp4l[783.065]: master offset       -333 s2 freq   +1323 path delay       396

    ptp4l[784.065]: master offset       -404 s2 freq   +1152 path delay       396

    ptp4l[785.065]: master offset       -381 s2 freq   +1054 path delay       396

    ptp4l[786.065]: master offset       -303 s2 freq   +1017 path delay       396

    ptp4l[787.065]: master offset       -297 s2 freq    +933 path delay       396

    ptp4l[788.065]: master offset        -19 s2 freq   +1121 path delay       396

    ptp4l[789.065]: master offset        316 s2 freq   +1451 path delay       396

    ptp4l[790.065]: master offset        373 s2 freq   +1603 path delay       396



    The s0, s1, s2 strings indicate the different clock servo states: s0 is unlocked, s1 is clock step and s2 is locked. Once the servo is in the locked state, the clock will not be stepped (only slowly adjusted). INITIALIZING, LISTENING, UNCALIBRATED and SLAVE are some of possible port states which change on the INITIALIZE, RS_SLAVE, MASTER_CLOCK_SELECTED events. The master offset value is the measured offset from the master in nanoseconds. This has decreased from 3409342692 to -373 indicating successful synchronization with master changing the port state from UNCALIBRATED to SLAVE.

Running Qbv/Time Aware Shaper:

Qbv functionality can be programmed using two ways

1)qbv_sched utility.

2) qdisc frame work.

1)qbv_sched utility

For Example:

qbv_sched -c ep /tmp/abc.cfg

This schedules Qbv on ep using the TSN configuration of abc.cfg present in tmp directory

qbv_sched ep

This schedules Qbv on ep using the default TSN configuration present in /etc/qbv.cfg

qbv_sched -g ep